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TMS320DM6431 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 227 page  1.2 Description TMS320DM6431 Digital Media Processor SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com • High-End CAN Controller (HECC) (Multiplexed With Other Device Functions) • 10/100 Mb/s Ethernet MAC (EMAC) • Packages: – IEEE 802.3 Compliant – 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch – Supports Media Independent Interface (MII) – 376-Pin Plastic BGA Package – Management Data I/O (MDIO) Module (ZDU Suffix), 1.0-mm Ball Pitch • Three Pulse Width Modulator (PWM) Outputs • 0.09-µm/6-Level Cu Metal Process (CMOS) • On-Chip ROM Bootloader • 3.3-V and 1.8-V I/O, 1.2-V Internal (-3/-3Q/-3S) • Individual Power-Savings Modes • Applications: • Flexible PLL Clock Generators – Digital Media • IEEE-1149.1 (JTAG™) – Networked Media Encode Boundary-Scan-Compatible – Video Imaging • Up to 111 General-Purpose I/O (GPIO) Pins The TMS320C64x+™ DSPs (including the TMS320DM6431 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6431 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6431 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32K-byte (KB) memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data/memory memory/cache (L1D) consists of a 64KB memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 64KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. 2 TMS320DM6431 Digital Media Processor Submit Documentation Feedback |
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