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TMS320C6748EZWT3 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6748EZWT3 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 273 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320C6748 SPRS590F – JUNE 2009 – REVISED MARCH 2014 TMS320C6748™ Fixed- and Floating-Point DSP 1 TMS320C6748 Fixed- and Floating-Point DSP 1.1 Features 1 – 2 SP x DP → DP Every Three Clocks • 375- and 456-MHz C674x Fixed- and Floating- Point VLIW DSP – 2 DP x DP → DP Every Four Clocks • C674x Instruction Set Features • Fixed-Point Multiply Supports Two 32 x 32- Bit Multiplies, Four 16 x 16-Bit Multiplies, or – Superset of the C67x+ and C64x+ ISAs Eight 8 x 8-Bit Multiplies per Clock Cycle, – Up to 3648 MIPS and 2746 MFLOPS and Complex Multiples – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Instruction Packing Reduces Code Size – 8-Bit Overflow Protection – All Instructions Conditional – Bit-Field Extract, Set, Clear – Hardware Support for Modulo Loop Operation – Normalization, Saturation, Bit-Counting – Protected Mode Operation – Compact 16-Bit Instructions – Exceptions Support for Error Detection and • C674x Two-Level Cache Memory Architecture Program Redirection – 32KB of L1P Program RAM/Cache • Software Support – 32KB of L1D Data RAM/Cache – TI DSP BIOS™ – 256KB of L2 Unified Mapped RAM/Cache – Chip Support Library and DSP Library – Flexible RAM/Cache Partition (L1 and L2) • 128KB of RAM Shared Memory • Enhanced Direct Memory Access Controller 3 • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and (EDMA3): DDR2 Interfaces) – 2 Channel Controllers • Two External Memory Interfaces: – 3 Transfer Controllers – EMIFA – 64 Independent DMA Channels • NOR (8- or 16-Bit-Wide Data) – 16 Quick DMA Channels • NAND (8- or 16-Bit-Wide Data) – Programmable Transfer Burst Size • 16-Bit SDRAM with 128-MB Address Space • TMS320C674x Floating-Point VLIW DSP Core – DDR2/Mobile DDR Memory Controller with one – Load-Store Architecture with Nonaligned of the following: Support • 16-Bit DDR2 SDRAM with 256-MB Address – 64 General-Purpose Registers (32-Bit) Space – Six ALU (32- and 40-Bit) Functional Units • 16-Bit mDDR SDRAM with 256-MB Address • Supports 32-Bit Integer, SP (IEEE Single Space Precision/32-Bit) and DP (IEEE Double • Three Configurable 16550-Type UART Modules: Precision/64-Bit) Floating Point – With Modem Control Signals • Supports up to Four SP Additions Per Clock, – 16-Byte FIFO Four DP Additions Every Two Clocks – 16x or 13x Oversampling Option • Supports up to Two Floating-Point (SP or • LCD Controller DP) Reciprocal Approximation (RCPxP) and • Two Serial Peripheral Interfaces (SPIs) Each with Square-Root Reciprocal Approximation Multiple Chip Selects (RSQRxP) Operations Per Cycle • Two Multimedia Card (MMC)/Secure Digital (SD) – Two Multiply Functional Units: Card Interfaces with Secure Data I/O (SDIO) • Mixed-Precision IEEE Floating-Point Multiply Interfaces Supported up to: • Two Master and Slave Inter-Integrated Circuits – 2 SP x SP → SP Per Clock ( I2C Bus™) – 2 SP x SP → DP Every Two Clocks 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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