UCC39151

SLUS184A – FEBRUARY 1999 – REVISED OCTOBER 2001

2

www.ti.com

description (continued)

When the output current is below the fault level, the output MOSFET is switched on with a nominal on-resistance

of 0.15

Ω. When the output current exceeds the fault level, but is less than the maximum sourcing level, the

switch is turned off, and remains off for 50 times the programmed fault time. When the output current reaches

the maximum sourcing level, the MOSFET transitions from a switch to a constant current source.

Input voltage, VIN

15.5 V

. . . . . . . . . . . . . . . . . . . .

(VOUT – VIN)

0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . .

FAULT sink current

50 mA

. . . . . . . . . . . . . . . . . . .

FAULT voltage

–0.3 to 8 V

. . . . . . . . . . . . . . . . . . .

Output current, VOUT

Self limiting

. . . . . . . . . . . .

TTL input voltage

. . . . . . . . . . . . . . . .

Storage temperature

–65

°C to 150°C

. . . . . . . . .

Junction temperature

–55

°C to 150°C

. . . . . . . .

Lead temperature (soldering 10 seconds) 300

°C

† Stresses beyond those listed under “absolute maximum ratings”

may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any

other conditions beyond those indicated under “recommended

operating

conditions”

is

not

implied.

Exposure

to

absolute-maximum-rated conditions for extended periods may

affect device reliability. Currents are positive into, negative out of the

specified terminal.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

SHTDWN

VIN

VIN

NC

GND*

GND*

GND*

GND*

EGND*

B3

B2

B1

FAULT

VOUT

VOUT

NC

GND*

GND*

GND*

GND*

NC

CT

IMAX

B0

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SHTDWN

VIN

VIN

GND*

EGND*

B3

B2

B1

FAULT

VOUT

VOUT

GND*

GND*

CT

IMAX

B0

DIL (N) or SOIC (DP)

PACKAGE

(TOP VIEW)

NC = no connection

* Pin 5 on the N and DP packages (and pin 9 on the PWP package)

serves as the lowest impedance to the electrical ground. Pins 4, 12

and 13 on the DP package (and pins 5, 6, 7, 8, 17, 18, 19, and 20 on

the PWP package) serve as heatsink/ground. These pins should be

connected to large etch areas to help dissipate heat. On the N

package, pins 4, 12 and 13 are not connected.

AVAILABLE OPTIONS

TA

PACKAGES

TA

SOIC (DP)

{

DIL (N)

TSSOP (PWP)

{

0

°C to 70°C

UCC39151DP

UCC39151N

UCC39151PWP

† The DP and PWP packages are available taped and reeled. Add TR suffix to

device type (e.g. UCC39151DPTR) to order quantities of 2500 (DP) or 2000

(PWP) devices per reel.