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UCC29950DR Datasheet(PDF) 9 Page - Texas Instruments |
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UCC29950DR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 68 page  UCC29950 www.ti.com SLUSC18A – SEPTEMBER 2014 – REVISED MARCH 2015 Electrical Characteristics (continued) –40°C < TJ < 125°C (1), VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBULK, PFC OUTPUT VOLTAGE PFC output overvoltage protection (auto VBULK(ovp) 1.06 1.10 1.14 V recovery) VBULK(reg) VBULK regulation set-point 0.907 0.940 0.973 V VBULK(llc_start) LLC operation start threshold 0.70 0.73 0.77 V VBULK(llc_stop) LLC operation stop threshold 0.45 0.49 0.53 V AC1, AC2, AC LINE SENSING FOR PFC RAC1 AC1 pin resistance to AGND AC1 pin 45 60 71 k Ω RAC2 AC2 pin resistance to AGND AC2 pin 45 60 71 Force current into AC1 or AC_DET is active HIGH when IAC is below this IAC(det) (4) (5) AC2 pins. Unused pin input 7.03 7.48 7.93 level at 0 V. Force current into AC1 or PFC stage stops 100 ms after IAC is at or below IAC(low_falling) (4) (5) AC2 pins. Unused pin input 7.03 7.48 7.93 this level at 0 V. Force current into AC1 or PFC stage is allowed to start when IAC is at or IAC(low_rising) (4) (5) AC2 pins. Unused pin input 8.04 8.55 9.1 above this level at 0 V. µARMS Force current into AC1 or IAC(high_falling) (4) (5 PFC stage restarts if IAC falls below this level. No AC2 pins. Unused pin input 30.7 32.0 33.3 ) soft-start at 0 V. Force current into AC1 or IAC(high_rising) (4) (5) PFC stage stops if IAC is at or above this level AC2 pins. Unused pin input 31.8 33.1 34.4 at 0 V. Force current into AC1 or PFC and LLC stages stop if IAC is at or above IAC(halt) (4) (5) AC2 pins. Unused pin input 32.8 34.2 35.6 this level at 0 V. PFC_CS, PFC CURRENT SENSE Maximum voltage at PFC_CS pin, (ignoring signal ripple due to inductor ripple current) that VPFCCS(cav_max) determines maximum power delivered. Used to –200 –225 –250 determine RCS_PFC. (see PFC Stage Current mV Sensing Figure 13 and Figure 6) VBULK pin = 800 mV, VPFCCS(max) Maximum voltage at PFC_CS pin –570 –800 –950 |VAC1 – VAC2| = VAC_PEAK (6) PFC_GD, PFC GATE DRIVER VHI(pfc_2mA) PFC_GD high level IO(PFC_GD) = –2 mA 11.5 11.8 12.0 V VHI(pfc_75mA) PFC_GD high level IO(PFC_GD) = –75 mA 8.5 9.5 10.5 RPFC(gd_hi) PFC_GD pull-up resistance IO(PFC_GD) = –50 mA 14 25 Ω RPFC(gd_lo) PFC_GD pull-down resistance IO(PFC_GD) = 75 mA 4.4 10 Capacitive load of 1.0 nF on tR(pfc) PFC_GD rise time 30 45 PFC_GD pin, 20% to 80% ns Capacitive load of 1.0 nF on tF(pfc) PFC_GD fall time 10 25 PFC_GD pin, 20% to 80% Includes dithering of ±2 kHz fPFC Switching frequency 87 98 109 kHz at nominal 333-Hz rate. (4) These are specified at 25°C. The relative levels for these specifications track each other. The equivalent line voltages are given in Table 3, assuming a source impedance of 9.3 M Ω. (5) This is the current into the AC1 or AC2 pins. (6) Tested at peak of line voltage or 90° from zero crossing. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: UCC29950 |
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