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UCC29002DGK Datasheet(PDF) 3 Page - Texas Instruments |
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UCC29002DGK Datasheet(HTML) 3 Page - Texas Instruments |
3 / 30 page 1 2 3 4 8 7 6 5 CS− CS+ VDD GND CSO LS EAO ADJ CSO LS EAO ADJ 8 7 6 5 1 2 3 4 CS− CS+ VDD GND 3 UCC29002, UCC29002-1, UCC39002 www.ti.com SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016 Product Folder Links: UCC29002 UCC39002 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions D or DGK Package 8-Pin SOIC or VSSOP Top View P Package 8-Pin PDIP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. ADJ 5 O Adjust amplifier output. This is the buffered output of the error amplifier block to adjust output voltage of the power supply being controlled. This pin must always be connected to a voltage equal to or greater than VEAO + 1 V. CS– 1 I Current sense amplifier inverting input. CS+ 2 I Current sense amplifier noninverting input. CSO 8 O Current sense amplifier output. EAO 6 O Output for load share error amplifier. (Transconductance error amplifier.) GND 4 – Ground. Reference ground and power ground for all device functions. Return the device to the low current sense −path of the converter. LS 7 I/O Load share bus. Output of the load share bus driver amplifier. VDD 3 I Power supply providing bias to the device. Bypass with a good quality, low ESL 0.1-µF to 1-µF, maximum, capacitor as close to the VDD pin and GND as possible. |
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