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UCC2894 Datasheet(PDF) 9 Page - Texas Instruments |
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UCC2894 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 34 page UCC2891, UCC2892 UCC2893, UCC2894 SLUS542A − OCTOBER 2003 − REVISED JULY 2004 9 www.ti.com DETAILED PIN DESCRIPTIONS (continued) SYNC (pin 5) This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running frequency of the onboard oscillator T SYNC t TSW . The acceptable minimum pulse width of the synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than 1 * D MAX T SYNC where DMAX is set by RON and ROFF. If the pulse width of the synchronization signal stays within these limits, the maximum operating duty ratio remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free running and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the 1 * D MAX T SYNC limit, the maximum operating duty cycle is defined by the synchronization pulse width. For more information on synchronization of the UCC2891 family refer to the Functional Description section of this datasheet. GND (pin 6) This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2891 family. CS (pin 7) This is a direct input to the PWM and current limit comparators of the UCC2891 family of controllers. The CS pin should never be connected directly across the current sense resistor (RCS) of the power converter. A small, customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected to the CS pin (RF, CF). Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slope compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT) of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the timing capacitor. This time interval is 1 * D MAX T SW long and represents the guaranteed off time of the main power switch. RSLOPE (pin 8) A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation current. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representation of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope compensation is proportional to this current flowing through RSLOPE. Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized. For more information on how to program the internal slope compensation refer to the Setup Guide section of this datasheet. |
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