 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMDS181RGZR Datasheet(PDF) 5 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
TMDS181RGZR Datasheet(HTML) 5 Page - Texas Instruments |
|
|
5 / 59 page  5 TMDS181, TMDS181I www.ti.com SLASE75C – AUGUST 2015 – REVISED JULY 2016 Product Folder Links: TMDS181 TMDS181I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) (H) Logic high (pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (pin strapped to GND through 65 kΩ resistor); (for mid-level = No connect) (2) G = Ground, I = Input, O = Output, P = Power Pin Functions(1) PIN TYPE(2) DESCRIPTION NAME NO. VCC 13, 43 P 3.3 V power supply VDD 14, 23, 24, 37, 48 P 1.2 V power supply GND 7, 19, 41, 30, Thermal pad G Ground MAIN LINK INPUT PINS IN_D2p/n 2, 3 I Channel 2 differential input IN_D1p/n 5, 6 I Channel 1 differential input IN_D0p/n 8, 9 I Channel 0 differential input IN_CLKp/n 11, 12 I Clock differential input MAIN LINK OUTPUT PINS (FAIL SAFE) OUT_D2n/p 34, 35 O TMDS data 2 differential output OUT_D1n/p 31, 32 O TMDS data 1 differential output OUT_D0n/p 28, 29 O TMDS data 0 differential output OUT_CLKn/p 25, 26 O TMDS data clock differential output HOT PLUG DETECT PINS HPD_SRC 4 O Hot plug detect output to source side HPD_SNK 33 I Hot plug detect input from sink side AUDIO RETURN CHANNEL AND DDC PINS SPDIF_IN ARC_OUT 45 44 I/O SPDIF signal input Audio return channel output SDA_SRC SCL_SRC 47 46 I/O Source side TMDS port bidirectional DDC data line Source side TMDS port bidirectional DDC clock line SDA_SNK SCL_SNK 39 38 I/O Sink side TMDS port bidirectional DDC data line Sink side TMDS port bidirectional DDC clock line CONTROL PINS OE 42 I Operation enable/reset pin OE = L: Power-down mode OE = H: Normal operation Internal weak pull up: Resets device when transitions from H to L SIG_EN 17 I Signal detector circuit enable SIG_EN = L: Signal detect circuit disabled: SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters standby mode. Internal weak pull down PRE_SEL 20 I 3 level De-emphasis control when I2C_EN/PIN = Low. PRE_SEL = L: –2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High de-emphasis is controlled through I2C EQ_SEL/A0 21 I 3 level Input receive equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB at 3 GHz When I2C_EN/PIN = High address bit 1 Note: 3 level for pin strap programming but 2 level when I2C address I2C_EN/PIN 10 I I2C_EN/PIN = High; puts device into I2C Control Mode I2C_EN/PIN = Low; puts device into pin strap mode Note: I2C CSR is addressable at all times, but features that can be controlled by pin strapping can only be changed by I2C when this pin is pulled high SCL_CTL 15 I I2C clock signal Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C |
Similar Part No. - TMDS181RGZR |
|
Similar Description - TMDS181RGZR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
