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UCC3809PTR-2 Datasheet(PDF) 3 Page - Texas Instruments |
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UCC3809PTR-2 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 23 page 3 UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 PIN DESCRIPTIONS FB: This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250 W on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND. GND: Reference ground and power ground for all functions. OUT: This pin is the high current power driver output. A minimum series gate resistor of 3.9 W is recommended to limit the gate drive current when operating with high bias voltages. REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47 mF ceramic capacitor. RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.74 · (CT + 27pF) · RT1). The positive threshold of the internal oscillator is sensed through inactive timing resistor RT2 which connects to pin RT2 and timing capacitor CT. RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.74 · (CT + 27pF) · RT2). The negative threshold of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor CT. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6 µA current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and IVDD < 100 mA. VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1 mF ceramic capacitor. ELECTRICAL CHARACTERISTICS: Unless otherwise specified, CVREF = 0.47 mF, VDD = 12V. TA =TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Soft Start Section ISS VDD = 16V, VSS = 0V; –40 °Cto +85°C –4.9 –7.0 –9.1 mA VDD = 16V, VSS = 0V; < –40°C; >+85°C –4.0 –7.0 –10.0 mA VSS Low VDD = 7.5V, ISS = 200 mA 0.2 V Shutdown Threshold 0.44 0.48 0.52 V Oscillator Section Frequency RT1 = 10k, RT2 = 4.32k, CT = 820pF 90 100 110 kHz Frequency Change with Voltage VDD = 10V to 15V 0.1 %/V CT Peak Voltage 3.33 V CT Valley Voltage 1.67 V CT Peak to Peak Voltage 1.54 1.67 1.80 V Output Section Output VSAT Low IOUT = 80mA (dc) 0.8 1.5 V Output VSAT High IOUT = –40mA (dc), VDD – OUT 0.8 1.5 V Output Low Voltage During UVLO IOUT = 20mA (dc) 1.5 V Minimum Duty Cycle VFB =2V 0 % Maximum Duty Cycle 70 % Rise Time COUT = 1nF 35 ns Fall Time COUT = 1nF 18 ns Note 1. Ensured by design. Not 100% production tested. |
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