6

UCC1857

UCC2857

UCC3857

4

2

1

12

VIN

IAC

UVLO

13.75V / 10V

CRMS

RMS DETECT

AND

CONDITIONING

X

÷

X

MULT

10

VA–

3.0V

0.5V

ZERO POWER

9

SS

10

µA

11

VAO

7

CA–

ENBL

1.0V

ALWAYS

ON

SD

7.5V

REF

VREF

5

REF GOOD

3

ENBL

VOLTAGE AMP

13

PKLMT

CURRENT AMP

PEAK LIMIT

COMP

8

MOUT

CAO

20

CT

19

RT

OSCILLATOR

TOGGLE

F/F

Q

Q

PWM

LATCH

Q

R

R

S

R

PWM

COMP

SD

SD

TRAILING

EDGE

DELAY

DELAY

15

VD

14

MOSDRV

16

IGDRV1

18

IGDRV2

17 PGND

6

AGND

DRIVER

DRIVER

DRIVER

VD

VD

APPLICATION INFORMATION (continued)

BLOCK DIAGRAM

through the transformer and the output rectifier. It can

be seen that the¸

÷ operation on the primary side of the

circuit is that of a boost converter and UCC3857 pro-

vides input current programming using average current

mode control to achieve unity power factor. The trans-

former turns ratio can be used to get the required level

of output voltage (higher or lower than the peak line volt-

age). The transformer also provides galvanic isolation

for the output voltage.

Power stage optimization involves design and selection

of components to meet the performance and cost objec-

tives.

These include the power switches, transformer

and inductor design.

The choice of IGBTs is based on their advantage over

MOSFETs at higher voltages. For universal line opera-

tion, the voltage stress on the push-pull switches can

approach 1000V. However, the slow turn-off of IGBTs

can contribute high switching losses and the use of

MOSFET (QA) helps turn the IGBTs off with zero voltage

across them (ZCS turn-off). This is accomplished by

keeping QA on (beyond the turn-off of Q1 or Q2 – see

Fig. 1 for waveforms) to allow the inductor current to di-

vert from IGBT to MOSFET while the IGBT is turning off

and still maintain zero volts. The MOSFET delay time

(TD1) effectively adds to the boost inductor charge pe-

riod. The voltage stress of the MOSFET is half the stress

of the IGBTs under normal operating conditions. How-

ever, QA can see much higher voltage stress under

start-up and short circuit conditions as the converter oper-

ates in a flyback mode then. For different operating re-

quirements or constraints (e.g. single North American line

operation), the choice of switching components may be

different (e.g. MOSFETs for Q1 and Q2 and no QA) as

the voltage stress is different. In that case, UCC3857 can

still be used without using the MOSDRV output.

Transformer design is very critical in this topology. The

push-pull transformer must have minimal leakage induc-

tance between the primary and secondary windings. Simi-

larly, the leakage between the two primary windings must

be minimized. In practice, it is hard to achieve both tar-

gets without using sophisticated construction techniques

such as interleaving, use of foils etc. In many cases, it

may be beneficial to use a planar transformer to achieve

these objectives. The effects of higher leakage induc-

tance include higher voltage stresses, ringing, power

losses and loss of available duty cycle. The high voltage

levels make it difficult to design effective snubber circuits

for this leakage induced ringing.

UDG-98218