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TLV70130DBVR Datasheet(PDF) 2 Page - Texas Instruments |
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TLV70130DBVR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 14 page TLV701xx SBVS161 – NOVEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS(1) PRODUCT VOUT TLV701xxyyyz XX is nominal output voltage (for example, 30 = 3.0 V) YYY is Package Designator Z is Package Quantity (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT MIN MAX Voltage(2) IN –0.3 24 V Current source OUT Internally limited Operating junction, TJ –40 +150 °C Temperature Storage, Tstg –65 +150 °C Human body model (HBM) 2 kV QSS 009-105 (JESD22-A114A) Electrostatic Discharge Rating(3) Charged device model (CDM) 500 V QSS 009-147 (JESD22-C101B.01) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLV701XX THERMAL METRIC(1) DBV UNITS 5 PINS θJA Junction-to-ambient thermal resistance 213.1 θJCtop Junction-to-case (top) thermal resistance 110.9 θJB Junction-to-board thermal resistance 97.4 °C/W ψJT Junction-to-top characterization parameter 22.0 ψJB Junction-to-board characterization parameter 78.4 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated |
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