TLV5639C datasheet(6/25 Pages) TI1

Part #	TLV5639C

Description	2.7-V TO 5.5-V LOW-POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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OPERATING CHARACTERISTICS

DIGITAL INPUT TIMING REQUIREMENTS

TLV5639C

TLV5639I

SLAS189C – MARCH 1999 – REVISED JANUARY 2004

over recommended operating free-air temperature range, V

ref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted)

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

1

3

Output settling time, full

RL = 10 kΩ, CL = 100 pF,

ts(FS)

µs

scale

see note (1)

Slow

3.5

7

Fast

0.5

1.5

Output settling time, code

RL = 10 kΩ, CL = 100 pF,

ts(CC)

µs

to code

see note (2)

Slow

1

2

Fast

6

10

RL = 10 kΩ, CL = 100 pF,

SR

Slew rate

V/µs

see note (3)

Slow

1.2

1.7

Glitch energy

DIN = 0 to 1, fCLK = 100 kHz, CS = VDD

5

nV-S

SNR

Signal-to-noise ratio

73

78

SINAD

Signal-to-noise + distortion

61

67

fs = 480 kSPS,

fout = 1 kHz,

fB = 20 kHz,

dB

THD

Total harmonic distortion

69

62

RL = 10 kΩ,

CL = 100 pF

Spurious free dynamic

SFDR

63

74

range

(1)

Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change of

0x020 to 0xFDF or 0xFDF to 0x020.

(2)

Settling time is the time for the output signal to remain within

± 0.5 LSB of the final measured value for a digital input code change of

one count.

(3)

Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

MIN

NOM

MAX

UNIT

tsu(CS-WE)

Setup time, CS low before negative WE edge

15

ns

tsu(D)

Setup time, data ready before positive WE edge

10

ns

tsu(R)

Setup time, REG ready before positive WE edge

20

ns

th(DR)

Hold time, data and REG held valid after positive WE edge

5

ns

tsu(WE-LD)

Setup time, positive WE edge before LDAC low

5

ns

twH(WE)

Pulse duration, WE high

20

ns

tw(LD)

Pulse duration, LDAC low

23

ns

6

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