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TLV5619CDWR Datasheet(PDF) 5 Page - Texas Instruments |
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TLV5619CDWR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 26 page  www.ti.com TIMING REQUIREMENTS TLV5619 SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004 REFERENCE INPUT (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vref Reference input voltage See (1) 0 VDD-1.5 V Ri Reference input resistance 10 M Ω Ci Reference input capacitance 5 pF Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see (2)) 60 dB Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc at -3 dB 1.4 MHz DIGITAL INPUTS (D0-D11, CS, WE, LDAC, PD) IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V 1 µA Ci Input capacitance 8 pF (1) Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes. (2) Reference feedthrough is measured at the DAC output with an input code = 0x000 and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at 1 kHz. POWER SUPPLY PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5-V Supply 1.6 3 IDD Power supply current No load, All inputs 0 V or VDD mA 3-V Supply 1.44 2.7 Power down supply current 0.01 10 µA ANALOG OUTPUT DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5-V Vref(REFIN) = 2.048 V, 8 12 V/µs Supply CL = 100 pF, Vref(REFIN) =1.024 V, SR Slew rate RL = 10 kΩ VO from 10% to 90% 3-V 6 9 V/µs VO from 90% to 10% Supply Output settling time (full ts To ±0.5 LSB, R L = 10 kΩ, CL = 100 pF, See (1) 1 3 µs scale) Glitch energy DIN = all 0s to all 1s 5 nV-s fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, 5-V S/N Signal to noise 65 78 fOUT = 1 kHz, RL = 10 kΩ , TA = 25°C, See (2) Supply 5-V 58 67 Supply fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, S/(N+D) Signal to noise + distortion fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2) 3-V 58 69 dB Supply fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, Total harmonic distortion 68 60 fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2) Spurious free dynamic fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, 60 72 range fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2) (1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 32 to 4063 or 4063 to 32. Limits are ensured by design and characterization, but are not production tested. (2) 1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V. DIGITAL INPUTS MIN NOM MAX UNIT tsu(CS-WE) Setup time, CS low before positive WE edge 13 ns tsu(D) Setup time, data ready before positive WE edge 9 ns th(D) Hold time, data held after positive WE edge 0 ns tsu(WE-LD) Setup time, positive WE edge before LDAC low 0 ns twh(WE) Pulse width, WE high 25 ns tw(LD) Pulse width, LDAC low 25 ns 5 |
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