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TLV5606CD Datasheet(PDF) 5 Page - Texas Instruments |
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TLV5606CD Datasheet(HTML) 5 Page - Texas Instruments |
5 / 28 page TLV5606 2.7V TO 5.5V LOW POWER 10BIT DIGITALTOANALOG CONVERTERS WITH POWER DOWN SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 5 WWW.TI.COM operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ts(FS) Output settling time, full scale RL = 10 kΩ, CL = 100 pF, Fast 3 5.5 s ts(FS) Output settling time, full scale RL = 10 kΩ, See Note 11 CL = 100 pF, Slow 9 20 µs ts(CC) Output settling time, code to code RL = 10 kΩ, CL = 100 pF, Fast 1 µs ts(CC) Output settling time, code to code RL = 10 kΩ, See Note 12 CL = 100 pF, Slow 2 µs SR Slew rate RL = 10 kΩ, CL = 100 pF, Fast 3.6 V/ s SR Slew rate RL = 10 kΩ, See Note 13 CL = 100 pF, Slow 0.9 V/ µs Glitch energy Code transition from 0x7FF to 0x800 10 nV−s S/N Signal to noise fs = 400 KSPS fout = 1.1 kHz, 62 dB S/(N+D) Signal to noise + distortion fs = 400 KSPS fout = 1.1 kHz, RL = 10 kΩ CL = 100 pF, 60 dB THD Total harmonic distortion RL = 10 kΩ, CL = 100 pF, BW = 20 kHz −61 dB Spurious free dynamic range BW = 20 kHz 68 dB NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS−FS) Setup time, CS low before FS ↓ 10 ns tsu(FS−CK) Setup time, FS low before first negative SCLK edge 8 ns tsu(C16−FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16−CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH Pulse duration, SCLK high 25 ns twL Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) Pulse duration, FS high 20 ns |
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