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UC1526 Datasheet(PDF) 5 Page - Texas Instruments |
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UC1526 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 10 page TTL, open-drain CMOS, and open-collector voltage com- parators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC ______ LOW in- itiates a discharge cycle in the oscillator. Pulling SHUTDOWN ____________ LOW immediately inhibits all PWM output pulses. Holding RESET _______ LOW discharges the soft-start capacitor. The logic threshold is +1.1V at +25°C. Noise immunity can be gained at the expense of fan-out with an external 2k pull-up resistor to +5V. Oscillator The oscillator is programmed for frequency and dead time with three components: RT, CT and RD. Two waveforms are generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The follow- ing procedure is recommended for choosing timing val- ues: 1. With RD = 0 (pin 11 shorted to ground) select values for RT and CT from Figure 7 to give the desired oscillator period. Remember that the frequency at each driver out- put is half the oscillator frequency, and the frequency at the +VC terminal is the same as the oscillator frequency. 2. If more dead time is required, select a large value of RD. At 40kHz dead time increases by 400ns/ Ω . 3. Increasing the dead time will cause the oscillator fre- quency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value. The UC1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a fre- quency 10% slower than the sync frequency. A periodic LOW logic pulse approximately 0.5 µs wide at the SYNC ______ pin will then lock the oscillator to the external frequency. Multiple devices can be synchronized together by pro- gramming one master unit for the desired frequency and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master, and all SYNC ______ terminals are likewise con- nected to the SYNC ______ pin of the master. Slave RT termi- nals are left open or connected to VREF. Slave RD terminals may be either left open or grounded. Error Amplifier The error amplifier is a transconductance design, with an output impedance of 2M Ω . Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 100pF, the amplifier has an open-loop pole at 800Hz. The input connections to the error amplifier are deter- mined by the polarity of the switching supply output volt- age. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 6B. Output Drivers The totem-pole output drivers of the UC1526 are de- signed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +VC, as required. Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the +VC terminal to ground during switching. To limit the re- sulting current spikes a small resistor in series with pin 14 is always recommended. The resistor value is deter- mined by the driver supply voltage, and should be chosen for 200mA peak currents. UC1526 UC2526 UC3526 Figure 5. Oscillator Connections and Waveforms Figure 4. Digital Control Port Schematic APPLICATIONS INFORMATION (cont.) 5 |
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