TLV2548CPW datasheet(8/49 Pages) TI1

Part #	TLV2548CPW

Description	2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

Download	49 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

Logo

8 / 49 page

TLV2544, TLV2548

2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER

SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN

SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

normal sampling

When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short

sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input

source resistance is high.

extended sampling

CSTART − An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order

to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined

and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling

period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal

to the minimum t(SAMPLE). In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon

as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has

become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time

requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion

period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function

is useful for an application that requires:

D The use of an extended sampling period to accommodate different input source impedance

D The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed

number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance

at lower supply voltage.

Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command

to read the conversion result or by simply selecting the next channel number for conversion. Since the device

has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data

output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low

transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of

the ADC qualifies this condition and successfully puts the ADC back to its normal sampling mode. This can be

viewed in Figure 9.

Table 3. Sample and Convert Conditions

CONDITIONS

SAMPLE

CONVERT

CSTART

CS = 1

(see Figures

11 and 18)

No sampling clock (SCLK) required. Sampling

period is totally controlled by the low time of CSTART.

The high-to-low transition of CSTART (when CS=1)

starts the sampling of the analog input signal. The low

time of CSTART dictates the sampling period. The

low-to-high transition of CSTART ends sampling

period and begins the conversion cycle. (Note: this

trigger only works when internal reference is selected

for conversion modes 01, 10, and 11.)

1) If the internal clock OSC is selected a maximum

CS

CSTART = 1

FS = 1

SCLK is required. Sampling period is programmable

under normal sampling. When programmed to sample

under short sampling, 12 SCLKs are generated to

complete sampling period. 24 SCLKs are generated

when programmed for long sampling. A command set

to configure the device requires 4 SCLKs thereby ex-

tending to 16 or 28 SCLKs respectively before conver-

1) If the internal clock OSC is selected a maximum

conversion time of 3.86

µs can be achieved.

2) If external SCLK is selected, conversion time is

tconv = 14 × DIV/f(SCLK), where DIV can be 1, 2, or

4.

FS

CSTART = 1

CS = 0

tending to 16 or 28 SCLKs respectively before conver-

sion takes place. (Note: Because the ADC only

bypasses a valid channel select command, the user

can use select channel 0, 0000b, as the SDI input

when either CS or FS is used as trigger for conversion.

The ADC responds to commands such as SW power-

down, 1000b.)

Similar Part No. - TLV2548CPW

Manufacturer	Part #	Datasheet	Description
Texas Instruments	TLV2548CPW	648Kb / 39P	[Old version datasheet] 2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
	TLV2548CPW	1Mb / 48P	[Old version datasheet] Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO
	TLV2548CPWG4	1Mb / 48P	[Old version datasheet] Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO
	TLV2548CPWR	1Mb / 48P	[Old version datasheet] Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO
	TLV2548CPWRG4	1Mb / 48P	[Old version datasheet] Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO

More results

Similar Description - TLV2548CPW

Manufacturer	Part #	Datasheet	Description
Texas Instruments	TLV2544	648Kb / 39P	[Old version datasheet] 2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
	TLV1504	638Kb / 42P	[Old version datasheet] 2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
	TLV2541	426Kb / 26P	[Old version datasheet] 2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
	TLV2541	1Mb / 33P	[Old version datasheet] 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
	TLV2542IDR	1Mb / 31P	[Old version datasheet] 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
	TLV2541IDR	1Mb / 30P	[Old version datasheet] 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
	TLV2544Q	623Kb / 37P	[Old version datasheet] 3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
	TLV2544Q	863Kb / 41P	[Old version datasheet] 3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
	TLV5616	845Kb / 28P	[Old version datasheet] 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
	TLV5627C	258Kb / 19P	[Old version datasheet] 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

More results

TLV2548CPW Datasheet(PDF) 8 Page - Texas Instruments

TLV2548CPW Datasheet(HTML) 8 Page - Texas Instruments

Similar Part No. - TLV2548CPW

Similar Description - TLV2548CPW

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL