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TLV2471ID Datasheet(PDF) 6 Page - Texas Instruments |
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TLV2471ID Datasheet(HTML) 6 Page - Texas Instruments |
6 / 64 page www.ti.com ELECTRICAL CHARACTERISTICS (continued) OPERATING CHARACTERISTICS TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA SLOS232E – JUNE 1999 – REVISED JULY 2007 At specified free-air temperature, VDD = 3V, unless otherwise noted. PARAMETER TEST CONDITIONS TA (1) MIN TYP MAX UNIT +25 °C 74 90 VDD = 2.7V to 6V, VIC = VDD/2, No load Full range 66 Supply voltage rejection ratio kSVR dB ( ΔVDD/ΔVIO) +25 °C 77 92 VDD = 3V to 5V, VIC = VDD/2, No load Full range 68 +25 °C 550 750 IDD Supply current (per channel) VO = 1.5V, No load μA Full range 800 +25 °C 350 1500 Supply current in shutdown IDD(SHDN) mode (TLV2470, TLV2473, TLV247xC Full range 2000 nA SHDN = 0V TLV2475) (per channel) TLV247xI Full range 4000 (1) Full range is 0 °C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C. At specified free-air temperature, VDD = 3V, unless otherwise noted. PARAMETER TEST CONDITIONS TA (1) MIN TYP MAX UNIT +25 °C 1.1 1.4 SR Slew rate at unity gain VO(PP) = 0.8V, CL = 150pF, RL= 10kΩ V/ μs Full range 0.6 f = 100Hz +25 °C 28 Equivalent input noise Vn nV/ √Hz voltage f = 1kHz +25 °C 15 Equivalent input noise In f = 1kHz +25 °C 0.405 pA/ √Hz current AV = 1 0.02% VO(PP) = 2V, Total harmonic THD+N RL= 10kΩ, AV = 10 +25 °C 0.1% distortion plus noise f = 1kHz AV = 100 0.5% t(on) Amplifier turn-on time +25 °C 5 μs RL= OPEN (2) t(off) Amplifier turn-off time +25 °C 250 ns Gain-bandwidth f = 10kHz, RL = 600Ω +25 °C 2.8 MHz product V(STEP)PP = 2V, 0.1% 1.5 AV = –1, CL = 10pF, 0.01% 3.9 RL = 10kΩ ts Settling time +25 °C μs V(STEP)PP = 2V, 0.1% 1.6 AV = –1, CL = 56pF, 0.01% 4 RL = 10kΩ Φm Phase margin RL = 10kΩ, CL = 1000pF +25 °C 61 ° Gain margin RL = 10kΩ, CL = 1000pF +25 °C 15 dB (1) Full range is 0 °C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C. (2) Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply current has reached half its final value. 6 Submit Documentation Feedback |
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