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DESCRIPTION (CONTINUED)

Differences Between TLK2201A, TLK2201AI, and TNETE2201

TLK2201A

TLK2201AI

SLLS572B – JUNE 2003 – REVISED SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

The primary application of these devices is to provide building blocks for point-to-point baseband data

transmission over controlled impedance media of 50

Ω or 75 Ω. The transmission media can be printed-circuit

board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent

upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2201A and TLK2201AI perform the data serialization, deserialization, and clock extraction functions for a

physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data

bandwidth over a copper or optical media interface.

The TLK2201A and TLK2201AI support both the defined 10-bit interface (TBI) and a reduced 5-bit interface

utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit

wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at

PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and

deserializes the data, outputting a parallel 10-bit data byte.

In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and

falling edge of the reference clock. The data is clocked most significant bit first, (bits 0–4 of the 8b/10b encoded

data) on the rising edge of the clock and the least significant bits (bits 5–9 of the 8b/10b encoded data) are

clocked on the falling edge of the clock.

The TLK2201A and TLK2201AI provide a comprehensive series of built-in tests for self-test purposes including

loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is

also supported.

The TLK2201A and TLK2201AI are housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD

package. Use of the PowerPAD package does not require any special considerations except to note that the

PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical

conductor. It is recommended that the TLK2201A and TLK2201AI PowerPADs be soldered to the thermal land

on the board.

The TLK2201A is characterized for operation from 0

°C to 70°C. The TLK2201AI is characterized for operation

from –40

°C to 85°C.

The TLK2201A and TLK2201AI use a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply

the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.

The TLK2201A and TLK2201AI are designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the

parallel output signal terminals, TXP, and TXN to be held in high-impedance state.

The TLK2201A and TLK2201AI are the functional equivalent of the TNETE2201. There are several differences

between the devices as noted below. Refer to Figure 12 in the application information section for an example of

a typical application circuit.

• The V

• The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The

TLK2201A and TLK2201AI uses these pins to provide added test capabilities. The capacitors, if present, do

not affect the operation of the device.

• No pulldown resistors are required on the TXP/TXN outputs.

AVAILABLE OPTIONS

PACKAGE

PLASTIC QUAD FLAT PACK (RCP)

0

°C to 70°C

TLK2201ARCP

–40

°C to 85°C

TLK2201AIRCP

2

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