©2002 Fairchild Semiconductor Corporation

Application Note 7510 Rev. A1

Driving constraints for this work were:

5. The SPICE device equations should not be modified.

6. Global temperature should be included.

7. All modes and levels of power MOSFET operation should

be modeled.

8. The sub-circuit should be empirically developed to

complement the device physics and the source code

algorithms.

9. The sub-circuit should be acceptable to a circuit design

user.

10. Parameter extraction should require little or no iteration.

Temperature Modeling

Use is made of voltage controlled voltage sources and

model statements in order to form master/slave circuit

relationships. In this manner, resistors can often be used to

establish a first and second order temperature correction

where direct PSpice algorithms will not permit thermal

modeling.

The primary device for gate controlled positive or negative

current flow is provided by Mos1 which is defined by the level

1 model MOSMOD. The second order effect of threshold

Model MOSMOD also defines Mos2 but with a 1 percent

scaling.

separate resistors, rather than being included with the MOS-

FETs. In this manner, 1st and 2nd order temperature effects

may be added as described by model RDSMOD.

The thermal variation of KP as provided by the source code

is a satisfactory representation. However, the threshold

voltage of Mos1 must be modified by the voltage dependent

tive voltage in series with the gate as a function of tempera-

MOD.

Avalanche breakdown of the MOSFET is provided by the

vided by model RBKMOD. High current voltage drops are

provided by RS of the model DBKMOD including thermal

sensitivity.

The power MOSFET being modelled contains a third quad-

rant diode as a fabrication consequence, and it is repre-

current IS, the transit time for stored charge effects TT, the

body diode series resistance RS, temperature dependence

of this resistor TRS1 and TRS2, and the MOSFET output

capacitance CJO.

The inductances associated with the device terminals are

The effective series resistance associated with the gate is

MOSFET output capacitance is provided by model DBD-

MOD as described above. Feedback capacitance is provided

used for this function to provide a square root dependency

with drain to source voltage. The voltage dependent voltage

voltage is imposed across the feedback capacitor while forc-

ing the feedback current flow into the gate node. It is further

necessary that the ideality factor N of model DPLCAPMOD

be made large to exclude forward diode conduction during

third quadrant operation of the MOSFET.

to source voltage becomes sufficiently negative. This switch-

ing is implemented by the switch S1A. Model S1AMOD

defines the switch closed resistance, open resistance, and

the gate to source voltages through which the fully on to fully

off transition occurs. During this transition, switch S1B also

transitions from fully off to fully on. Switch S1B is defined by

open.

Switch S2A is defined by model S2AMOD for the on resis-

tance, off resistance, and drain to gate voltage transition

range. During this transition switch S2B also transitions as

defined by model S2BMOD. Voltage controlled voltage gen-

when switch S2A is open.

In order to facilitate DC convergence, PSPICE provides a

minimum conductance between all nodes as defined by the

PSPICE analysis options. In order to assure that a floating

gate initial condition will not exist should a modeler drive

from a current source, a very large gate to source resistor

required.

All sub-circuit elements are treated as being independent of

temperature if they are not otherwise defined.

Gate propagation effects [15], radiation effects, and inherent

VDMOS design deficiencies are not modelled. This is

discussed later.

All discussions apply equally to P channel although N

channel is discussed exclusively.

Applications

The sub-circuit combined with external circuitry may be

analyzed for many responses. Three circuits are modelled to

demonstrate the capability of the PSPICE sub-circuit model.

A synchronous rectifier producing 100 watts at 5 volts DC

from a 100KHz square wave demonstrates the ability to

handle the first and third quadrant regimes of two MOSFETs,

including conversion efficiency versus temperature. Calcu-

lated waveforms are presented, but they are unsupported by

measured data. The diode recovery waveform is modelled

Application Note 7510