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AN4137 Datasheet(PDF) 10 Page - Fairchild Semiconductor

Part # AN4137
Description  Design Guidelines
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

AN4137 Datasheet(HTML) 10 Page - Fairchild Semiconductor

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AN4137
APPLICATION NOTE
10
©2003 Fairchild Semiconductor Corporation
and RB is the internal feedback bias resistor of FPS, which is
typically 2.8k
Ω and R
1, RD, RF, CF and CB are shown in fig-
ure 12.
Figure 13. CCM flyback converter control-to output trans-
fer function variation for different input voltages
Figure 14. CCM flyback converter control-to output trans-
fer function variation for different loads
Figure 15. DCM flyback converter control-to output trans-
fer function variation for different loads
When the input voltage and the load current vary over a wide
range, it is not easy to determine the worst case for the feed-
back loop design. The gain together with zeros and poles
vary according to the operating condition. Moreover, even
though the converter is designed to operate in CCM or at the
boundary of DCM and CCM in the minimum input voltage
and full load condition, the converter enters into DCM
changing the system transfer functions as the load current
decreases and/or input voltage increases.
One simple and practical way to this problem is designing
the feedback loop for low input voltage and full load condi-
tion with enough phase and gain margin. When the converter
operates in CCM, the RHP zero is lowest in low input volt-
age and full load condition. The gain increases only about
6dB as the operating condition is changed from the lowest
input voltage to the highest input voltage condition under
universal input condition. When the operating mode changes
from CCM to DCM, the RHP zero disappears making the
system stable. Therefore, by designing the feedback loop
with more than 45 degrees phase margin in low input voltage
and full load condition, the stability over all the operating
ranges can be guaranteed.
The procedure to design the feedback loop is as follows
(a) Determine the crossover frequency (fc). For CCM mode
flyback, set fc below 1/3 of right half plane (RHP) zero to
minimize the effect of the RHP zero. For DCM mode fc can
be placed at a higher frequency, since there is no RHP zero.
(b) When an additional LC filter is employed, the crossover
frequency should be placed below 1/3 of the corner fre-
quency of the LC filter, since it introduces a -180 degrees
phase drop. Never place the crossover frequency beyond the
corner frequency of the LC filter. If the crossover frequency
is too close to the corner frequency, the controller should be
designed to have a phase margin greater than 90 degrees
when ignoring the effect of the post filter.
(c) Determine the DC gain of the compensator (wi/wzc) to
cancel the control-to-output gain at fc.
(d) Place a compensator zero (fzc) around fc/3.
(e) Place a compensator pole (fpc) above 3fc.
Figure 16. Compensator design
v
FB
ˆ
v
o1
ˆ
---------
-
w
i
s
-----
1s w
zc
+
11 w
pc
+
---------------------------
=
(35)
where w
i
R
B
R
1RDCF
----------------------- , w
zc
1
R
F
R
1
+
()C
F
--------------------------------- , w
pc
1
R
BCB
---------------
=
=
=
0 dB
20 dB
-20 dB
-40 dB
40 dB
10Hz
100Hz
10kHz
1kHz
1Hz
100kHz
Low input voltage
High input voltage
f
p
f
p
f
z
f
z
f
rz
frz
0 dB
20 dB
-20 dB
-40 dB
40 dB
10Hz
100Hz
10kHz
1kHz
1Hz
100kHz
Heavy load
Light load
f
p
f
p
f
z
f
rz
f
rz
0 dB
20 dB
-20 dB
-40 dB
40 dB
10Hz
100Hz
10kHz
1kHz
1Hz
100kHz
Heavy load
Light load
f
p
f
p
f
z
f
z
0 dB
20 dB
-20 dB
-40 dB
40 dB
10Hz
100Hz
10kHz
1kHz
1Hz
100kHz
Control to output
f
p
f
z
f
rz
Compensator
Loop gain T
f
zc
f
pc
f
c


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