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DS89C450-MNG Datasheet(PDF) 7 Page - Dallas Semiconductor

Part # DS89C450-MNG
Description  Ultra-High-Speed Flash Microcontrollers
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS89C450-MNG Datasheet(HTML) 7 Page - Dallas Semiconductor

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Note 15: The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/
maximum external clock speed. The term “1/tCLCL” used in the AC Characteristics variable timing table is determined from the
following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.
External Clock Speed
4X/
2X
CD1
CD0
Number of External Clock
Cycles per System Clock
(1/tCLCL)
Min
Max
1
0
0
1/4
5MHz
8.25MHz
0
0
0
1/2
10MHz
16.5MHz
X
0
1
Reserved
X
1
0
1
See AC Characteristics
See AC Characteristics
X
1
1
1024
See AC Characteristics
See AC Characteristics
Note 16: External MOVX instruction times are dependent upon the setting of the MD2, MD1, and MD0 bits in the clock control register. The
terms “tSTC1, tSTC2, tSTC3” used in the variable timing table above are calculated through the use of the table given below.
MD2
MD1
MD0
MOVX Instruction Time
tSTC1
tSTC2
tSTC3
tSTC4
tSTC5
0
0
0
2 Machine Cycles
0 tCLCL
0 tCLCL
0 tCLCL
0 tCLCL
0 tCLCL
0
0
1
3 Machine Cycles
2 tCLCL
1 tCLCL
0 tCLCL
0 tCLCL
1 tCLCL
0
1
0
4 Machine Cycles
6 tCLCL
1 tCLCL
0 tCLCL
0 tCLCL
1 tCLCL
0
1
1
5 Machine Cycles
10 tCLCL
1 tCLCL
0 tCLCL
0 tCLCL
1 tCLCL
1
0
0
6 Machine Cycles
14 tCLCL
5 tCLCL
4 tCLCL
1 tCLCL
1 tCLCL
1
0
1
7 Machine Cycles
18 tCLCL
5 tCLCL
4 tCLCL
1 tCLCL
1 tCLCL
1
1
0
8 Machine Cycles
22 tCLCL
5 tCLCL
4 tCLCL
1 tCLCL
1 tCLCL
1
1
1
9 Machine Cycles
26 tCLCL
5 tCLCL
4 tCLCL
1 tCLCL
1 tCLCL
Note 17: Maximum load capacitance (to meet the above timing) for Port 0, ALE,
PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance are dependent upon the frequency of the selected crystal.
Figure 1. Nonpage Mode Timing
ALE
Port 0
Port 2
LSB
DATA
XTAL1
PSEN
RD
MSB
MSB
MSB
MSB
MSB
WR
LSB
LSB
LSB
LSB
DATA
MOVX
MOVX
OPCODE
tCLCL
tAVLL2
tLHLL
tWLWH
tLLAX2
tLLWL
tLLPL
tLLAX
tLLIV
tAVIV0
tPXIX
tPLPH
tPLIV
tAVLL3
tLLAX3
tRLRH
tPLAZ
tWHLH
tWHQX
tQVWX
tAVIV2
tAVDV2
tAVWL2
tPXIZ
tAVLL
tLLDV
tAVDV0
tRHDX
tRHDZ
tRLDV
tAVWL0


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