Electronic Components Datasheet Search |
|
TLK1201ARCP Datasheet(PDF) 6 Page - Texas Instruments |
|
TLK1201ARCP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 24 page www.ti.com Data Reception Receiver Clock Select Mode td(S) td(S) td(H) td(H) K28.5 DXX.X DXX.X DXX.X K28.5 DXX.X RBC0 RBC1 SYNC RD(0-9) td(H) td(S) K28.5 DXX.X DXX.X DXX.X K28.5 DXX.X RBC0 SYNC RD(0-9) TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007 The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with receive byte clocks (RBC0 and RBC1). There are two modes of operation for the parallel bus: 1) the 10-bit (TBI) mode and 2) 5-bit (DDR) mode. When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1) full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate clock is available on RBC0; see Table 1. Table 1. Mode Selection RECEIVE BYTE CLOCK MODESEL RBCMODE MODE TLK1201A TLK1201AI 0 0 TBI half-rate 30–65 MHz 30–65 MHz 0 1 TBI full-rate 60–130 MHz 60–130 MHz 1 0 DDR 60–130 MHz 60–130 MHz 1 1 DDR 60–130 MHz 60–130 MHz In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data is valid on the rising edge of RBC1. See the timing diagram shown in Figure 2. Figure 2. Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode) In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode. See the timing diagram shown in Figure 3. Figure 3. Synchronous Timing Characteristics Waveforms (TBI Full-Rate Mode) In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1 is low impedance. The data is clocked bit 0 first, and aligned to the rising edge of RBC0. See the timing diagram shown in Figure 4. 6 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP |
Similar Part No. - TLK1201ARCP_16 |
|
Similar Description - TLK1201ARCP_16 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |