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TLK2226GEA Datasheet(PDF) 2 Page - Texas Instruments |
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TLK2226GEA Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 52 page  www.ti.com TLK2226 SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006 The TLK2226 has six channels of SERDES each with 5 bit busses clocked double data rate (DDR). The parallel interface accepts un-encoded or 5-bit wide encoded data aligned to both the rising and falling edge of the transmit clock. The data is clocked low-order bits first, (i.e. bits 0–4 of the 8b/10b encoded data) on the rising edge of the transmit clock and the high-order bits (i.e. bits 5–9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The receive path interface is clocked in the same manner. The TLK2226 supports two modes that can repeat data from a channel’s serial receiver to the adjacent channel’s serial transmitter: serial repeater mode and retiming repeater mode. In serial repeater mode, the clock/data recovery (CDR) function will lock onto the incoming data stream and will pass this data stream over to the adjacent channel to be retransmitted. In serial repeater mode, the data stream stays in the same clock domain as the incoming data; there is no clock tolerance compensation function performed to align the data stream to the reference clock domain. In retiming repeater mode, the CDR function will lock onto the incoming data stream but the data will be deserialized and passed through the CTC FIFO and then serialized for transmission on the adjacent channel. In both repeater modes, the received data for Channel A is retransmitted on the output for channel B while the received data for Channel B is retransmitted on the output for Channel A. Likewise, Channel C is paired with Channel D, and Channel E is paired with Channel F. The repeater modes can be enabled on a channel by channel basis through the use of register control bits programmed through the MDIO interface. The recovered data clock frequency can be aligned to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that will insert or drop Idle 20-bit IDLE codes as needed in the absence of data. The received data for all channels are aligned to a single receive data clock that is a buffered version of the reference clock. The TLK2226 supports a selectable IEEE802.3z compliant 8b/10b encoder/decoder in all its 1.25Gbps modes of operation, and a IEEE802 compliant 4b/5b encoder/decoder in its 125Mbps mode of operation. The TLK2226 supports selectable RTBI and RGMII interface to supervision ASIC. The TLK2226 automatically locks onto incoming data without the need to pre-lock. Detection of whether the incoming data stream is at 1.25 Gbps or 125 Mbps data rate is automatic. A comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification is provided. An IEEE 1149.1 JTAG port is also supported to aid in board manufacturing test. This device is housed in a small form factor 15 × 15 mm, 196-pin, BGA with 1,0 mm ball pitch and is characterized to support the commercial temperature range of 0 °C to 70°C. Expect the TLK2226 to consume less than 1.5 W, when operating at 1.25 Gbps. The TLK2226 is designed to be hot plug capable. A power-on reset puts the parallel side output signal pins in a high-impedance state during power-up as well as pulls both TX+ and TX– to VDDA through 500 Ω. 2 Submit Documentation Feedback |
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