8

Description of Operation

A simplified block schematic is shown in Figure 2. The follow-

ing description is intended to provide the user with sufficient

information to be able to understand the effects that the

external components and signal conditions have on the out-

puts of the integrated circuit.

nominally 0.1µF. The clamp circuit A1 will prevent the input

signal on pin 2 going any more negative than 1.5V, the value

tive part of the video waveform, will be clamped at 1.5V. The

capacitor during the remaining portion of the H line, approxi-

mately 58µs for a 15.75kHz timebase. From I • t = C • V, the

video time-constant can be calculated. It is important to note

that the charge taken from the capacitor during video must

be replaced during the sync tip time, which is much shorter,

(ratio of x 12.5). The corresponding current to restore the

charge during sync will therefore be an order of magnitude

tip crushing. For this reason, the internal series resistance

has been minimized and external high resistance values in

series with the input coupling capacitor should be avoided.

The user can exercise some control over the value of the

input time constant by introducing an external pull-up resis-

tance from pin 2 to the 5V supply. The maximum voltage

For a net discharge current greater than zero, the resistance

should be greater than 450k. This will have the effect of

increasing the time constant and reducing the degree of pic-

explained later.

The signal is processed through an active 3 pole filter (F1)

designed for minimum ripple with constant phase delay. The

filter attenuates the color burst by 24dB and eliminates fast

transient spikes without sync crushing. An external filter is

not necessary. The filter also amplifies the video signal by

6dB to improve the detection accuracy. Note that the filter

to supply voltage variation are derived on the chip. Refer-

of 1.7V nominal. Consequently, it can be seen that the exter-

rejection.

Comparator C2 on the input to the sample and hold block

(S/H) compares the leading and trailing edges of the sync.

initiates the timing one-shots for gating the sample and hold

circuits. The sample of the sync tip is delayed by 0.8µs to

enable the actual sample of 2µs to be taken on the optimum

section of the sync. pulse tip. The acquisition time of the cir-

cuit is about three horizontal lines. The double poly CMOS

technology enables long time constants to be achieved with

small high quality on-chip capacitors. The back porch voltage

is similarly derived from the trailing edge of sync, which also

serves to cut off the tip sample if the gate time exceeds the

tip period. Note that the sample and hold gating times will

The 50% level of the sync tip is derived, through the resistor

This comparator has built in hysteresis to avoid false trigger-

ing. The output of C2 is a digital 5V signal which feeds the

C/S output buffer B1 and the other internal circuit blocks, the

vertical, back porch and odd/even functions.

The vertical circuit senses the C/S edges and initiates an

integrator which is reset by the shorter horizontal sync pulses

but times out the longer vertical sync. pulse widths. The

time-out period being inversely proportional to the timing cur-

rent. The vertical output pulse is started on the first serration

pulse in the vertical interval and is then self-timed out. In the

absence of a serration pulse, an internal timer will default the

start of vertical.

The back porch is triggered from the sync tip trailing edge

and initiates a one-shot pulse. The period of this pulse is

The odd/even circuit (O/E) comprises of flip flops which track

the relationship of the horizontal pulses to the leading edge

of the vertical output, and will switch on every field at the start

of vertical. Pin 7 is high during the odd field.

Loss of video signal can be detected by monitoring the C/S

output. The 50% level of the previous video signal will remain

held on the S/H capacitors after the input video signal has

gone and the input on pin 2 has defaulted to the clamp volt-

age. Consequently the C/S output will remain low longer than

the normal vertical pulse period. An external timing circuit

could be used to detect this condition.

EL4581