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TLC5943 Datasheet(PDF) 8 Page - Texas Instruments |
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TLC5943 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 40 page www.ti.com TLC5943 SBVS101 – DECEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME PWP RHB I/O DESCRIPTION SIN 5 2 I Serial data input for grayscale and brightness control data. Schmitt buffer input. Serial data shift clock for GS shift register and BC shift register. Schmitt buffer input. The shift register is selected by BCSEL. Data present on the SIN pin are shifted into the shift register SCLK 4 1 I selected by BCSEL with the rising edge of the SCLK pin. Data in the selected shift register are shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB data of the selected register appears on SOUT. Data in the Grayscale and Brightness shift register are moved to the respective first data latch XLAT 3 32 I with a low-to-high transition of this pin. Shift register and data latch select. Schmitt buffer input. When BCSEL is low, Grayscale shift BCSEL 6 3 I register and first data latch are selected. When BCSEL is high, Brightness Control shift register and first data latch are selected. BCSEL should not be changed while SCLK is high. Reference clock for Grayscale PWM control. Schmitt buffer input. If BLANK is low, then each GSCLK 25 24 I rising edge of GSCLK increments the grayscale counter for PWM control. Blank (all constant current outputs off). Schmitt buffer input. When BLANK is high, all constant current outputs (OUT0 through OUT15) are forced off, the Grayscale counter is reset to '0', and BLANK 2 31 I the Grayscale PWM timing controller is initialized. When BLANK is low, all constant current outputs are controlled by the Grayscale PWM timing controller. Constant current value setting. OUT0 through OUT15 sink constant current is set to desired IREF 27 26 I/O value by connecting an external resistor between IREF and GND. Serial data output. This output is connected to Grayscale/Status Information shift register or SOUT 24 23 O Brightness Control shift register. The connected register is selected by BCSEL. XERR 23 22 O Error output. Open-drain output. XERR goes low when LOD or TEF is detected. OUT0 7 4 O Constant current output. OUT1 8 5 O Constant current output OUT2 9 6 O Constant current output OUT3 10 7 O Constant current output OUT4 11 8 O Constant current output OUT5 12 9 O Constant current output OUT6 13 10 O Constant current output OUT7 14 11 O Constant current output OUT8 15 14 O Constant current output OUT9 16 15 O Constant current output OUT10 17 16 O Constant current output OUT11 18 17 O Constant current output OUT12 19 18 O Constant current output OUT13 20 19 O Constant current output OUT14 21 20 O Constant current output OUT15 22 21 O Constant current output VCC 28 27 — Power-supply voltage GND 1 30 — Power ground XTEST 26 25 I Factory test pin. XTEST must be connected to VCC or GND. 12, 13, NC — — No internal connection 28, 29 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5943 |
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