7

6

SER IN

8

2

10

1

9

SRCK

5

4

12

3

11

G

RCK

0

CLR

1

DRAIN0

0

DRAIN1

DRAIN10

0

DRAIN11

0

0

MCU

CLR

10 V

SRCK

SER IN

RCK

G

GND

DRAIN

5 V

V

CC

I

D

R

Output

C = 30 pF

(see Note A)

L

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9

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7 Parameter Measurement Information

A.

Figure 11. Resistive-Load Test Circuit

Figure 12. Voltage Waveforms

Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12

that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock,

indicating the transfer of data to the output buffers at that time.