Supertex inc.

does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

8

HV7100

(The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline

Doc.# DSFP-HV7100

B072413

14-Lead SOIC (Narrow Body) Package Outline (NG)

8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch

Symbol

A

A1

A2

b

D

E

E1

e

h

L

L1

L2

θ

θ1

Dimension

(mm)

MIN 1.35* 0.10

1.25

0.31 8.55* 5.80* 3.80*

1.27

BSC

0.25

0.40

1.04

REF

0.25

BSC

NOM

-

-

-

-

8.65

6.00

3.90

-

-

-

-

MAX 1.75

0.25 1.65* 0.51 8.75* 6.20* 4.00*

0.50

1.27

JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.

* This dimension is not specified in the JEDEC drawing.

Drawings are not to scale.

Supertex Doc. #: DSPD-14SOICNG, Version F041309.

Top View

Side View

View A-A

View B

A

A

Seating

Plane

14

1

Seating

Plane

Gauge

Plane

L

L1

L2

θ1

θ

View B

h

h

b

A A2

A1

e

E

E1

D

Note 1

(Index Area

D/2 x E1/2)

Note:

1.

This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be:

a molded mark/identifier; an embedded metal marker; or a printed indicator.