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TLC5618IDR Datasheet(PDF) 6 Page - Texas Instruments |
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TLC5618IDR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS156G – JULY 1997 – REVISED APRIL 2001 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref(REFIN) = 2.048 V (unless otherwise noted) (continued) reference input (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 0 VDD– 2 V Ri Input resistance 10 M Ω Ci Input capacitance 5 pF Reference feedthrough REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) – 60 dB Reference input bandwidth (f 3 dB) REFIN = 0 2 V + 1 024 V dc Slow 0.5 MHz Reference input bandwidth (f – 3 dB) REFIN = 0.2 Vpp + 1.024 V dc Fast 1 MHz NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at 1 kHz. digital inputs (DIN, SCLK, CS) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD ±1 µA IIL Low-level digital input current VI = 0 V ±1 µA Ci Input capacitance 8 pF power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD Power supply current VDD = 5.5 V, No load Slow 0.6 1 mA IDD Power supply current No load, All inputs = 0 V or VDD Fast 1.6 2.5 mA Power down supply current D13 = 0 (see Table 2) 1 µA operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref(REFIN) = 2.048 V (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR+ Output slew rate positive CL = 100 pF, RL 10 kΩ Vref(REFIN) = 2.048 V, TA =25°C Slow 0.3 0.5 V/ µs SR+ Output slew rate, positive RL = 10 kΩ, Code 32 to Code 4096, TA = 25°C, VO from 10% to 90% Fast 2.4 3 V/ µs SR Output slew rate negative CL = 100 pF, RL 10 kΩ Vref(REFIN) = 2.048 V, TA =25°C Slow 0.15 0.25 V/ µs SR– Output slew rate, negative RL = 10 kΩ, Code 4096 to Code 32, TA = 25°C, VO from 10% to 90% Fast 1.2 1.5 V/ µs t Output settling time To ±0.5 LSB, CL = 100 pF, Slow 12.5 µs ts Output settling time , RL = 10 kΩ, See Note 10 Fast 2.5 µs t () Output settling time, To ±0.5 LSB, CL = 100 pF, Slow 2 µs ts(c) g, code-to-code , RL = 10 kΩ, See Note 11 Fast 2 µs Glitch energy DIN = All 0s to all 1s, f(SCLK) = 100 kHz CS = VDD, 5 nV–s S/(N+D) Signal to noise + distortion Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc, Input code = 10 0000 0000 78 dB NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 020 hex to 3FF hex or 3FF hex to 020 hex. 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. |
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