64K x 16 Static RAM
CY7C1021BV33
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05148 Rev. *A
Revised September 13, 2002
021BV33
Features
• 3.3V operation (3.0V–3.6V)
• High speed
— tAA = 10/12/15 ns
• CMOS for optimum speed/power
• Low Active Power (L version)
— 576 mW (max.)
• Low CMOS Standby Power (L version)
— 1.80 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
• Available in a 48-Ball Mini BGA package
Functional Description[1]
The CY7C1021BV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an au-
tomatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write opera-
tion (CE LOW, and WE LOW).
The CY7C1021BV is available in 400-mil-wide SOJ, standard
44-pin TSOP Type II, and 48-ball mini BGA packages.
WE
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21
23
24
NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
64K x 16
RAM Array
I/O1–I/O8
A7
A6
A5
A4
A3
A0
COLUMN DECODER
512 X 2048
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
Selection Guide
7C1021BV-8
7C1021BV-10
7C1021BV-12
7C1021BV-15
Maximum Access Time (ns)
810
12
15
Maximum Operating Current (mA)
Commercial
170
160
150
140
Industrial
190
180
170
160
Maximum CMOS Standby Current
(mA)
Commercial
55
5
5
L
0.500
0.500
0.500
0.500
Shaded areas contain advance information.
Note:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.