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CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 4 of 13
Table 1. Non-Contending Read/Write Control
Control
I/O
Operation
R/WLB
R/WUB
CE
OE
I/O0–I/O8
I/O9–I/O17
X
X
H
X
High Z
High Z
Deselected: Power-Down
L
L
L
X
Data In
Data In
Write to Both Bytes
L
H
L
L
Data In
Data Out
Write Lower Byte, Read Upper Byte
H
L
L
L
Data Out
Data In
Read Lower Byte, Write Upper Byte
L
H
L
H
Data In
High Z
Write to Lower Byte
H
L
L
H
High Z
Data In
Write to Upper Byte
H
H
L
L
Data Out
Data Out
Read to Both Bytes
H
H
L
H
High Z
High Z
High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs
Outputs
Function
CEL
CER
AddressL
AddressR
BUSYL
BUSYR
X
X
No Match
H
H
Normal
H
X
Match
H
H
Normal
X
H
Match
H
H
Normal
L
L
Match
Note 3
Note 3
Write Inhibit[4]
32-Bit Master/Slave Dual-Port Memory Systems
Table 3. Arbitration Results
Case
Port
Winning Port
Result
Left
Right
1
Read
Read
L
Both ports read
2
Read
Read
R
Both ports read
3
Read
Write
L
L port reads OK R port write inhibited
4
Read
Write
R
R port writes OK L port data may be invalid
5
Write
Read
L
L port writes OK R port data may be invalid
6
Write
Read
R
R port reads OK L port write inhibited
7
Write
Write
L
L port writes OK R port write inhibited
8
Write
Write
R
R port writes OK L port write inhibited
Notes:
3.
The loser of the port arbitration will receive BUSY = “L” (BUSYL or BUSYR = “L”). BUSYL and BUSYR cannot both be LOW simultaneously.
4.
Writes are inhibited to the left port when BUSYL is LOW. Writes are inhibited to the right port when BUSYR is LOW.
LEFT
RIGHT
R/W
BUSY
R/W
BUSY
R/W
BUSY
BUSY
R/W
CY7C133
CY7C143
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