LP3872, LP3875

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SNVS227H – FEBRUARY 2003 – REVISED JANUARY 2015

Feature Description (continued)

7.3.2 Load Voltage Sense

In applications where the regulator output is not very close to the load, LP3875 can provide better remote load

regulation using the SENSE pin. Figure 10 depicts the advantage of the SENSE option. LP3872 regulates the

voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop

across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 m

Ω, the

the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown

in Figure 10. If the sense option pin is not required, the SENSE pin must be connected to the OUT pin.

Figure 10. Improving Remote Load Regulation Using LP3875

7.3.3 Short-Circuit Protection

The LP3872 and LP3875 devices are short-circuit protected and in the event of a peak overcurrent condition, the

short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts

down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the

thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency.

7.3.4 Low Dropout Voltage

The LP387x devices feature an ultra-low-dropout voltage, typically 38 mV at 150-mA load current and 380 mV at

1.5-A load current.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

A CMOS Logic low level signal at the shutdown (SD) pin will turn off the regulator. The SD pin must be actively

terminated through a 10-k

Ω pullup resistor for a proper operation. If this pin is driven from a source that actively

pulls high and low (such as a CMOS rail to rail comparator), the pullup resistor is not required. This pin must be

7.4.2 Active Mode

When voltage at SD pin of the LP387x device is at logic high level, the device is in normal mode of operation.

7.4.3 ERROR Flag Operation

The LP3872 and LP3875 produces a logic low signal at the ERROR Flag pin when the output drops out of

regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The

timing diagram in Figure 11 shows the relationship between the ERROR flag and the output voltage. In this

example, the input voltage is changed to demonstrate the functionality of the ERROR Flag.

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