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THS4031, THS4032

SLOS224H – JULY 1999 – REVISED JUNE 2016

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Copyright © 1999–2016, Texas Instruments Incorporated

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.4 Thermal Information – THS4031

THS4031

UNIT

D (SOIC)

DGN (HVSSOP)

8 PINS

8 PINS

Junction-to-ambient thermal resistance

128.9

61.6

°C/W

Junction-to-case (top) thermal resistance

80.9

53.9

°C/W

Junction-to-board thermal resistance

69.2

43.2

°C/W

Junction-to-top characterization parameter

23.7

3.8

°C/W

Junction-to-board characterization parameter

68.8

42.9

°C/W

Junction-to-case (bottom) thermal resistance

n/a

14.5

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Thermal Information – THS4032

THS4032

UNIT

D (SOIC)

DGN (HVSSOP)

8 PINS

8 PINS

Junction-to-ambient thermal resistance

121.2

56.5

°C/W

Junction-to-case (top) thermal resistance

72.8

48.4

°C/W

Junction-to-board thermal resistance

61.4

37.7

°C/W

Junction-to-top characterization parameter

18.2

2.5

°C/W

Junction-to-board characterization parameter

61

37.5

°C/W

Junction-to-case (bottom) thermal resistance

n/a

9.9

°C/W

(1)

Full range = 0°C to 70°C for THS403xC and –40°C to 85°C for THS403xI suffix.

(2)

Full power bandwidth = slew rate / [

(3)

Slew rate is measured from an output level range of 25% to 75%.

PARAMETER

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE

BW

Small-signal bandwidth (–3

dB)

Gain = –1 or 2

100

MHz

90

Bandwidth for 0.1-dB

flatness

Gain = –1 or 2

50

MHz

45

2.3

MHz

7.2

SR

20-V step

Gain = –1

100

V/μs

5-V step

80

Settling time to 0.1%

5-V step

Gain = –1

60

ns

2.5-V step

45

Settling time to 0.01%

5-V step

Gain = –1

90

ns

2.5-V step

80