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S3C44B0X Datasheet(PDF) 2 Page - Samsung semiconductor |
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S3C44B0X Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 424 page  PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR 1-2 FEATURES Architecture • Integrated system for hand-held devices and general embedded applications. • 16/32-Bit RISC architecture and powerful instruction set with ARM7TDMI CPU core. • Thumb de-compressor maximizes code density while maintaining performance. • On-chip ICEbreaker debug support with JTAG- based debugging solution. • 32x8 bit hardware multiplier. • New bus architecture to implement Low-Power SAMBA II(SAMSUNG's ARM CPU embedded Micro-controller Bus Architecture). System Manager • Little/Big endian support. • Address space: 32Mbytes per each bank. (Total 256Mbyte) • Supports programmable 8/16/32-bit data bus width for each bank. • Fixed bank start address and programmable bank size for 7 banks. • Programmable bank start address and bank size for one bank. • 8 memory banks. - 6 memory banks for ROM, SRAM etc. - 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM) • Fully Programmable access cycles for all memory banks. • Supports external wait signal to expend the bus cycle. • Supports self-refresh mode in DRAM/SDRAM for power-down. • Supports asymmetric/symmetric address of DRAM. Cache Memory & internal SRAM • 4-way set associative ID(Unified)-cache with 8Kbyte. • The 0/4/8 Kbytes internal SRAM using unused cache memory. • Pseudo LRU(Least Recently Used) Replace Algorithm. • Write through policy to maintain the coherence between main memory and cache content. • Write buffer with four depth. • Request data first fill technique when cache miss occurs. Clock & Power Manager • Low power • The on-chip PLL makes the clock for operating MCU at maximum 66MHz. • Clock can be fed selectively to each function block by software. • Power mode: Normal, Slow, Idle and Stop mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL Idle mode: Stop the clock for only CPU Stop mode: All clocks are stopped • Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode. Interrupt Controller • 30 Interrupt sources ( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO ) • Vectored IRQ interrupt mode to reduce interrupt latency. • Level/edge mode on the external interrupt sources • Programmable polarity of edge and level • Supports FIQ (Fast Interrupt request) for very urgent interrupt request FEATURES (Continued) |
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