Philips Semiconductors

Product data sheet

PCA9548

2004 Sep 30

5

DEVICE ADDRESSING

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9548 is

shown in Figure 3. To conserve power, no internal pullup resistors

are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

A1 A0

0A2

SW00915

1

1

1

R/W

FIXED

HARDWARE SELECTABLE

Figure 3. Slave address

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9548, which will be stored

in the control register. If multiple bytes are received by the

PCA9548, it will save the last byte received. This register can be

B3

B2

B1

B0

SW00932

B7

B6

B5

B4

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL SELECTION BITS

(READ/WRITE)

65

4

2

1

0

73

Figure 4. Control register

CONTROL REGISTER DEFINITION

One or several SCx/SDx downstream pair, or channel, is selected

by the contents of the control register. This register is written after

the PCA9548 has been addressed. The 2 LSBs of the control byte

are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a stop

SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of

connection.

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

B7

B6

B5

B4

B3

B2

B1

B0

COMMAND

X

X

X

X

X

X

X

0

Channel 0

disabled

X

X

X

X

X

X

X

1

Channel 0

enabled

X

X

X

X

X

X

0

X

Channel 1

disabled

X

X

X

X

X

X

1

X

Channel 1

enabled

X

X

X

X

X

0

X

X

Channel 2

disabled

X

X

X

X

X

1

X

X

Channel 2

enabled

X

X

X

X

0

X

X

X

Channel 3

disabled

X

X

X

X

1

X

X

X

Channel 3

enabled

X

X

X

0

X

X

X

X

Channel 4

disabled

X

X

X

1

X

X

X

X

Channel 4

enabled

X

X

0

X

X

X

X

X

Channel 5

disabled

X

X

1

X

X

X

X

X

Channel 5

enabled

X

0

X

X

X

X

X

X

Channel 6

disabled

X

1

X

X

X

X

X

X

Channel 6

enabled

0

X

X

X

X

X

X

X

Channel 7

disabled

1

X

X

X

X

X

X

X

Channel 7

enabled

0

0

0

0

0

0

0

0

No channel

selected;

power-up/reset

default state

NOTE: Several channels can be enabled at the same time.

Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,

means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,

3, and 2 are enabled.

Care should be taken not to exceed the maximum bus capacitance.

RESET INPUT

The RESET input is an active-LOW signal which may be used to

recover from a bus fault condition. By asserting this signal LOW for

machine and will deselect all channels. The RESET input must be

POWER-ON RESET

point, the reset condition is released and the PCA9548 registers and

causing all the channels to be deselected.