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TFP101APZP Datasheet(PDF) 7 Page - Texas Instruments |
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TFP101APZP Datasheet(HTML) 7 Page - Texas Instruments |
7 / 21 page TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differential input sensitivity† 150 1560 mVp-p tps Analog input intra-pair (+ to -) differential skew (see Note 6) 0.4 tbit‡ tccs Analog Input inter-pair or channel-to-channel skew (see Note 6) 1 tpix§ tijit Worse case differential input clock jitter tolerance¶ (see Note 6) 50 ps tf1 Fall time of data and control signals#, || ST = Low, CL=5 pF ST = High, CL=10 pF 2.4 1.9 ns tr1 Rise time of data and control signals#, || ST = Low, CL=5 pF ST = High, CL=10 pF 2.4 1.9 ns tr2 Rise time of ODCK clock# ST = Low, CL=5 pF ST = High, CL=10 pF 2.4 1.9 ns tf2 Fall time of ODCK clock# ST = Low, CL=5 pF ST = High, CL=10 pF 2.4 1.9 ns tsu1 Setup time, data and control signal to falling edge of ODCK (OCK_INV = low)|| ST = Low, CL=5 pF ST = High, CL=10 pF 3.6 ns th1 Hold time, data and control signal to falling edge of ODCK (OCK_INV = low)|| ST = Low, CL=5 pF ST = High, CL=10 pF 3.6 ns tsu2 Setup time, data and control signal to rising edge of ODCK (OCK_INV = high)|| ST = Low, CL=5 pF ST = High, CL=10 pF 3.6 ns th2 Hold time, data and control signal to rising edge of ODCK (OCK_INV = high)|| ST = Low, CL=5 pF ST = High, CL=10 pF 3.1 ns fODCK ODCK frequency PIX = Low (1-PIX/CLK) 25 86 MHz fODCK ODCK frequency PIX = High (2-PIX/CLK) 12.5 43 MHz ODCK duty-cycle 40% 50% 60% tpd(PDL) Propagation delay time from PD low to Hi-Z outputs 9 ns tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs 9 ns tt(HSC) Transition time between DE transition to SCDT lowk 1e6 tpix tt(FSC) Transition time between DE transition to SCDT highk 1024 tpix td(st) Delay time, ODCK latching edge to QE[23:0] data output STAG = Low Pixs = High 0.25 tpix † Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. ‡ tbit is 1/10 the pixel time, tpix § tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. ¶ Measured differentially at 50% crossing using ODCK output clock as trigger. # Rise and fall times measured as time between 20% and 80% of signal amplitude. || Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1] kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. NOTE 6: By characterization Not Recommended for New Designs |
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