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TFP101A Datasheet(PDF) 10 Page - Texas Instruments |
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TFP101A Datasheet(HTML) 10 Page - Texas Instruments |
10 / 21 page TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description fundamental operation The TFP101/101A is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a TMDS compatible transmitter that receives 24 bit pixel data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a TMDS compatible receiver like the TI TFP101/101A to decode the serial bit stream back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to SXGA a high bandwidth receiver with good jitter and skew tolerance is required. TMDS pixel data and control signal encoding TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent and transmits the character that will minimize the number of transitions and approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The following table maps the received input data to appropriate TMDS input channel in a DVI compliant system. RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH INPUT CHANNEL OUTPUT PINS (VALID FOR DE = HIGH) Red[7:0] Channel – 2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel – 1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel – 0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW INPUT CHANNEL OUTPUT PINS (VALID FOR DE = LOW) CTL[3:2] Channel – 2 (Rx2 ±) CTL[3:2] CTL[1: 0] (see Note 6) Channel – 1 (Rx1 ±) CTL1 HSYNC, VSYNC Channel – 0 (Rx0 ±) HSYNC, VSYNC NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP101/101A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP101/101A output. The TFP101/101A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, i.e., state of DE. Not Recommended for New Designs |
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