FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 23 of 58
Bit 7: PS/2 Pull-up Enable
This bit is used to enable the internal PS/2 pull-up resistors on the SDATA and SCLK pins. Normally the output high level on
these pins is VCC, but note that the output will be clamped to approximately 1 Volt above VREG if the VREG Enable bit is set,
or if the Device Address is enabled (bit 7 of the USB Device Address Register, Figure 14-1).
1 = Enable PS/2 Pull-up resistors. The SDATA and SCLK pins are pulled up internally to VCC with two resistors of approximately
5k
Ω (see Section 25.0 for the value of RPS2).
0 = Disable PS/2 Pull-up resistors.
Bit 6: VREG Enable
A 3.3V voltage regulator is integrated on chip to provide a voltage source for a 1.5-k
Ω pull-up resistor connected to the D– pin
as required by the USB Specification. Note that the VREG output has an internal series resistance of approximately 200
Ω, the
external pull-up resistor required is approximately 1.3-k
Ω (see Figure 16-1).
1 = Enable the 3.3V output voltage on the VREG pin.
0 = Disable. The VREG pin can be configured as an input.
Bit 5: USB-PS/2 Interrupt Select
This bit allows the user to select whether an USB bus reset interrupt or a PS/2 activity interrupt will be generated when the
interrupt conditions are detected.
1 = PS/2 interrupt mode. A PS/2 activity interrupt will occur if the SDATA pin is continuously LOW for 128 to 256
µs.
0 = USB interrupt mode (default state). In this mode, a USB bus reset interrupt will occur if the single ended zero (SE0, D–
and D+ are LOW) exists for 128 to 256
µs.
See Section 21.3 for more details.
Bit 4: Reserved. Must be written as a ‘0’.
Bit 3: USB Bus Activity
The Bus Activity bit is a “sticky” bit that detects any non-idle USB event has occurred on the USB bus. Once set to HIGH by
the SIE to indicate the bus activity, this bit retains its logical HIGH value until firmware clears it. Writing a ‘0’ to this bit clears
it; writing a ‘1’ preserves its value. The user firmware should check and clear this bit periodically to detect any loss of bus
activity. Firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024-ms timer interrupt service routine is
normally used to check and clear the Bus Activity bit.
1 = There has been bus activity since the last time this bit was cleared. This bit is set by the SIE.
0 = No bus activity since last time this bit was cleared (by firmware).
Bit [2:0]: D+/D– Forcing Bit [2:0]
Forcing bits allow firmware to directly drive the D+ and D– pins, as shown in Table 13-1. Outputs are driven with controlled
edge rates in these modes for low EMI. For forcing the D+ and D– pins in USB mode, D+/D– Forcing Bit 2 should be 0. Setting
D+/D– Forcing Bit 2 to ‘1’ puts both pins in an open-drain mode, preferred for applications such as PS/2 or LED driving.
Bit #
76543210
Bit Name
PS/2 Pull-up
Enable
VREG
Enable
USB Reset-
PS/2Activity
Interrupt
Mode
Reserved
USB
Bus Activity
D+/D– Forcing Bit
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Reset
00000000
Figure 13-1. USB Status and Control Register (Address 0x1F)
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