FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 26 of 58
Bit 7: STALL
1 = The SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if the mode bits
are set to ACK-IN. See Section 22.0 for the available modes.
0 = This bit must be set to LOW for all other modes.
Bit [6:5]: Reserved. Must be written to zero during register writes.
Bit 4: ACKed Transaction
The ACKed transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an
ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode Bit [3:0]
The EP1 and EP2 Mode Bits operate in the same manner as the EP0 Mode Bits (see Section 14.2).
14.4
USB Endpoint Counter Registers
There are three Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 14-4.
Bit 7: Data Toggle
This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the transmitted
Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
1 = DATA1
0 = DATA0
Bit 6: Data Valid
This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred. This
bit does not update for some endpoint mode settings. Refer to Table 22-3 for more details.
1 = Data is valid.
0 = Data is invalid. If enabled, the endpoint interrupt will occur even if invalid data is received.
Bit [5:4]: Reserved
Bit [3:0]: Byte Count Bit [3:0]
Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the
number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP
transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values
are 2 to 10 inclusive.
Bit #
76
5432
10
Bit Name
STALL
Reserved
ACKed
Transaction
Mode Bit
Read/Write
R/W
-
-
R/C
R/W
R/W
R/W
R/W
Reset
00
0000
00
Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16)
Bit #
76
5432
10
Bit Name
Data Toggle
Data Valid
Reserved
Byte Count
Read/Write
R/W
R/W
-
-
R/W
R/W
R/W
R/W
Reset
00
0000
00
Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15)
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