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TAS5709PHP Datasheet(PDF) 6 Page - Texas Instruments |
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TAS5709PHP Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 61 page  48-TERMINAL, HTQFP PACKAGE (TOP VIEW) SSTIMER OC_ADJ PLL_FLTP VR_ANA NC AVSS PLL_FLTM BST_A GVDD_OUT PVDD_A OUT_A RESET PVDD_A STEST DVDD DVSS GND VREG PVDD_D BST_D OUT_D AGND PVDD_D GVDD_OUT P0075-06 PHP Package (TopView) TAS5709 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TAS5709, TAS5709A SLOS599A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com PIN FUNCTIONS PIN TYPE 5-V TERMINATION DESCRIPTION (1) TOLERANT (2) NAME NO. AGND 30 P Analog ground for power stage AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 4 P High-side bootstrap supply for half-bridge A BST_B 43 P High-side bootstrap supply for half-bridge B BST_C 42 P High-side bootstrap supply for half-bridge C BST_D 33 P High-side bootstrap supply for half-bridge D DVDD 27 P 3.3-V digital power supply DVSSO 17 P Oscillator ground DVSS 28 P Digital ground GND 29 P Analog ground for power stage GVDD_OUT 5, 32 P Gate drive internal regulator output LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample-rate clock) MCLK 15 DI 5-V Pulldown Master clock input (1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5709 TAS5709A |
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