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TAS3108IADCPRG4 Datasheet(PDF) 11 Page - Texas Instruments

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Part # TAS3108IADCPRG4
Description  AUDIO DIGITAL SIGNAL PROCESSORS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TAS3108IADCPRG4 Datasheet(HTML) 11 Page - Texas Instruments

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3.8.1
2 channel I
2S Timing
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input/Output
T0034-04
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3108/TAS3108IA should not be commanded to unmute
until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration
change while a volume or bass or treble update is taking place can cause the update not to be completed
properly.
When the TAS3108/TAS3108IA is transmitting serial data, it uses the negative edge of SCLK to output a
new data bit. The TAS3108/TAS3108IA samples incoming serial data on the rising edge of SCLK. The
TAS3108/TAS3108IA only supports TDM, left justified, right justified, and I2S formats.
In 2 channel I2S timing, LRCLK is LOW when left channel data is transmitted and HIGH when right
channel data is transmitted. SCLK is a bit clock running at 64
× f
S, which clocks in each bit of the data.
There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on
the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3108/TAS3108IA masks unused trailing data-bit positions.
Figure 3-2. I2S 64-fS Format
Submit Documentation Feedback
Physical Characteristics
11
Not Recommended for New Designs


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