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LMK04906 Datasheet(PDF) 10 Page - Texas Instruments |
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LMK04906 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 113 page  LMK04906 SNAS589D – JUNE 2012 – REVISED MAY 2013 www.ti.com Electrical Characteristics (3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Min Typ Max Units Current Consumption ICC_PD Power Down Supply Current 1 3 mA All clock delays disabled, Supply Current with all clocks enabled CLKoutX_DIV = 1045, ICC_CLKS 410 470 mA (1) CLKoutX_TYPE = 1 (LVDS), PLL1 and PLL2 locked. CLKin0/0*, CLKin1/1*, and CLKin2/2* Input Clock Specifications Clock Input Frequency fCLKin 0.001 500 MHz (2) Clock Input Slew Rate SLEWCLKin 20% to 80% 0.15 0.5 V/ns (3) VIDCLKin 0.25 1.55 |V| AC coupled Clock Input CLKinX_BUF_TYPE = 0 (Bipolar) VSSCLKin 0.5 3.1 Vpp Differential Input Voltage (4) VIDCLKin 0.25 1.55 |V| AC coupled Figure 14 CLKinX_BUF_TYPE = 1 (MOS) VSSCLKin 0.5 3.1 Vpp AC coupled to CLKinX; CLKinX* AC coupled to Ground 0.25 2.4 Vpp Clock Input CLKinX_BUF_TYPE = 0 (Bipolar) VCLKin Single-ended Input Voltage AC coupled to CLKinX; CLKinX* AC (3) coupled to Ground 0.25 2.4 Vpp CLKinX_BUF_TYPE = 1 (MOS) DC offset voltage between VCLKin0-offset CLKin0/CLKin0* 20 mV CLKin0* - CLKin0 DC offset voltage between Each pin AC coupled VCLKin1-offset CLKin1/CLKin1* 0 mV CLKin0_BUF_TYPE = 0 (Bipolar) CLKin1* - CLKin1 DC offset voltage between VCLKin2-offset CLKin2/CLKin2* 20 mV CLKin2* - CLKin2 DC offset voltage between Each pin AC coupled VCLKinX-offset CLKinX/CLKinX* 55 mV CLKinX_BUF_TYPE = 1 (MOS) CLKinX* - CLKinX VCLKin-VIH High input voltage DC coupled to CLKinX; CLKinX* AC 2.0 VCC V coupled to Ground VCLKin-VIL Low input voltage 0.0 0.4 V CLKinX_BUF_TYPE = 1 (MOS) FBCLKin/FBCLKin* and Fin/Fin* Input Specifications AC coupled Clock Input Frequency fFBCLKin (CLKinX_BUF_TYPE = 0) 0.001 1000 MHz (3) MODE = 2 or 8; FEEDBACK_MUX = 6 AC coupled Clock Input Frequency fFin (CLKinX_BUF_TYPE = 0) 0.001 3100 MHz (3) MODE = 3 or 11 Single Ended AC coupled; VFBCLKin/Fin Clock Input Voltage 0.25 2.0 Vpp (CLKinX_BUF_TYPE = 0) (3) Slew Rate on CLKin AC coupled; 20% to 80%; SLEWFBCLKin/Fin 0.15 0.5 V/ns (3) (CLKinX_BUF_TYPE = 0) (1) Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Current Consumption / Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design. (2) CLKin0, CLKin1, and CLKin2 maximum is guaranteed by characterization, production tested at 200 MHz. (3) Guaranteed by characterization. (4) See DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY for definition of VID and VOD voltages. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMK04906 |
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