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LMK03000C Datasheet(PDF) 6 Page - Texas Instruments |
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LMK03000C Datasheet(HTML) 6 Page - Texas Instruments |
6 / 45 page LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 3 Electrical Specifications 3.1 Absolute Maximum Ratings (1) (2) (3) Parameter Symbol Ratings Units Power Supply Voltage VCC -0.3 to 3.6 V Input Voltage VIN -0.3 to (VCC + 0.3) V Storage Temperature Range TSTG -65 to 150 °C Lead Temperature (solder 4 s) TL +260 °C Junction Temperature TJ 125 °C (1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. (2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV. (3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 3.2 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Ambient Temperature TA -40 25 85 °C Power Supply Voltage VCC 3.15 3.3 3.45 V 3.3 Package Thermal Resistance Package θJA θJ-PAD (Thermal Pad) 48-Lead WQFN (1) 27.4° C/W 5.8° C/W (1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in the board layout. 6 Electrical Specifications Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033 LMK03033C |
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