LMK00101

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SNAS572C – JANUARY 2012 – REVISED MAY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1) (2) (3)

Parameter

Symbol

Ratings

Units

Core Supply Voltage

Vdd

-0.3 to 3.6

V

Output Supply Voltage

Vddo

-0.3 to 3.6

V

Input Voltage

-0.3 to Vdd + 0.3

V

Storage Temperature Range

-65 to 150

°C

Lead Temperature (solder 4 s)

+260

°C

Junction Temperature

+125

°C

(1)

"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2)

This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD

protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.

(3)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Units

Ambient Temperature

-40

25

85

°C

Core Supply Voltage

Vdd

2.375

3.3

3.45

V

Vddo

1.425

3.3

Vdd

V

(1)

PACKAGE THERMAL RESISTANCE

32-Lead WQFN

Package

Symbols

Ratings

Units

Thermal resistance from junction to ambient

50

° C/W

Thermal resistance from junction to case

20

° C/W

(2)

(1)

Specification assumes 5 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias

play a key role in improving the thermal performance of the QFN. For best thermal dissipation it is recommended that the maximum

number of vias be used on the board layout.

(2)

Case is defined as the DAP (die attach pad).

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