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UPD720130 Datasheet(PDF) 5 Page - NEC |
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UPD720130 Datasheet(HTML) 5 Page - NEC |
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5 / 44 page  Data Sheet S16302EJ3V0DS 5 µµµµPD720130 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Level Function XIN I 2.5 V Input System clock input or oscillator In XOUT O 2.5 V Output Oscillator out RESETB I 3.3 V Schmitt Input Low Asynchronous reset signaling MD(1:0) I 3.3 V Input Function mode setting IDECS(1:0)B O (I/O) 5 V tolerant Output Low IDE host chip select IDEA(2:0) O (I/O) 5 V tolerant Output IDE address bus IDEINT I (I/O) 5 V tolerant Input High IDE interrupt request from device to host IDEDAKB O (I/O) 5 V tolerant Output Low IDE DMA acknowledge IDEIORDY I (I/O) 5 V tolerant Input High IDE IO channel ready IDEIORB O (I/O) 5 V tolerant Output Low IDE IO read strobe IDEIOWB O (I/O) 5 V tolerant Output Low IDE IO write strobe IDEDRQ I (I/O) 5 V tolerant Input High IDE DMA request from device to host IDED(15:0) I/O 5 V tolerant I/O IDE data bus IDERSTB O (I/O) 5 V tolerant Output Low IDE reset from host to device DCC I (I/O) 3.3 V Input IDE controller operational mode setting DV(1:0) I (I/O) 3.3 V Input Device select CLC I (I/O) 3.3 V Input System clock setting PWR I (I/O) 3.3 V Input Bus powered /self-powered select CMB_BSY O (I/O) 3.3 V Output Combo IDE bus busy CMB_STATE I (I/O) 3.3 V Input Combo IDE bus state DPC O (I/O) 3.3 V Output Power control signaling for IDE device SDA I/O 3.3 V I/O Serial ROM data signaling SCL I/O 3.3 V I/O Serial ROM clock signaling VBUS I 5 V Schmitt Input Note VBUS monitoring DP I/O USB high speed D+ I/O USB’s high speed D+ signal DM I/O USB high speed D − I/O USB’s high speed D − signal RSDP O USB full speed D+ Output USB’s full speed D+ signal RSDM O USB full speed D − Output USB’s full speed D − signal RPU A USB Pull-up control USB’s 1.5 k Ω pull-up resistor control RREF A Analog Reference resistor SPD I (I/O) 3.3 V Input NEC private SMC I 3.3 V Input Scan mode control TEST(3:0) I 3.3 V Input Test mode setting Note VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. System must ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not exceeded. |
Similar Part No. - UPD720130 |
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Similar Description - UPD720130 |
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