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S5LS10106ASZWTQQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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S5LS10106ASZWTQQ1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 106 page  TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141F – AUGUST 2010 – REVISED JULY 2011 2 Device Overview 2.1 Terms and Acronyms Table 2-1. Terms and Acronyms Terms and Acronyms Description Comments ADC Analog To Digital Converter AHB Advanced High-performance Bus Part of the R4 core CCM-R4 CPU Compare Module for CortexTM-R4F CRC Cyclic Redundancy Check Controller DAP Debug Access Port DAP is an implementation of an ARM Debug Interface. DCAN Controller Area Network DMA Direct Memory Access DMM Data Modification Module ECC Error Correction Code EMIF External Memory Interface ESM Error Signaling Module ETM Embedded Trace Module FMzPLL Frequency-Modulated Zero-Pin Phase-Locked Loop FPLL FlexRay Phase-Locked Loop GIO General-Purpose Input/Output HET High-End Timer ICEPICK In Circuit Emulation TAP (Test Access Port) ICEPick can connect or isolate a module level TAP to or from a Selection Module higher level chip TAP. ICEPick was designed with both emulation and test requirements in mind. JTAG Joint Test Access Group IEEE Committee responsible for Test Access Ports LBIST Logic Built-In Self Test Test the integrity of R4 CPU LIN Local Interconnect Network VIM Vectored Interrupt Manager MibSPI Multi-Buffered Serial Peripheral Interface MPU Memory Protection Unit OSC Oscillator PBIST Programmable Built-In Self Test Test the integrity of SRAM PCR Peripheral Central Resource POM Parameter Overlay Module The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory external to the device. PSA Parallel Signature Analysis RTI Real-Time Interrupt RTP RAM Trace Port SCR Switch Central Resource SCI Serial Communication Interface SECDED Single Error Correction and Double Error Detection STC Self Test Controller SYS System Module TU Transfer Unit VBUS Virtual Bus One of the protocols that comprises CBA (Common Bus Architecture) VBUSP Virtual Bus-Pipelined One of the protocols that comprises CBA (Common Bus Architecture) Copyright © 2010–2011, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback focus.ti.com: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended For New Designs |
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