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PI4IOE5V9570UE Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI4IOE5V9570UE Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
8 / 11 page |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||| ||||||||||||||||| 2015-07-0044 PT0559 08/05/15 8 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I 2C bus e. Bus Transaction Writing to the port (output mode) To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0, the Write mode is entered. The device acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the device. Writes to P7 to P4 are ignored in the PI4IOE5V9570 as only P3 through P0 are available. The 4-bit data is presented on the port lines after it has been acknowledged by the device. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent. Reading from a port (input mode) All ports are outputs and cannot be used as inputs. When reading the device, the data returned is the port state at the pin. To read, the master (microcontroller) first addresses the slave device by setting the last bit of the byte containing the slave address to logic 1. The data byte that follows on the SDA is the value of the ports pins. There is no limit to the number of bytes read, and the state of the output port pins is updated at each acknowledge cycle. Logic 1 means that the port is HIGH. Logic 0 means that the port is LOW. When the PI4IOE5V9570 is read, P7 through P4 return logic ‘1’. f. Power-on reset When power is applied to VCC, an internal Power-On Reset (POR) holds the device in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the device registers and I 2C-bus/SMBus state machine initialize to their default states. Figure 6: Write to configuration registers Figure 7: Read from registers Note: Transfer can be stopped at any time by a STOP condition. |
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