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SN75DP139RGZT Datasheet(PDF) 6 Page - Texas Instruments |
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SN75DP139RGZT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 43 page SN75DP139 SLLS977E – APRIL 2009 – REVISED SEPTEMBER 2014 www.ti.com Table 1. Control Pin Lookup Table (continued) SIGNAL LEVEL(1) STATE DESCRIPTION VSadj 4.02 k Ω Output Voltage Driver output voltage swing precision control to aid with system compliance ±5% Swing Contol HPDINV H HPD Inversion HPD_SOURCE VOH =0.9V (typical) and HPD logic is inverted L HPD non- HPD_SOURCE VOH =3.2V (typical) and HPD logic is non-inverted inversion SRC H Edge Rate: SRC helps to slow down the rise and fall time. SRC =High adds ~60ps to the rise Slowest and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection (recommended setting) L Edge Rate: Slow SRC helps to slow down the rise and fall time. SRC =Low adds ~30ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection Hi-Z Edge Rate Leaving the SRC pin High Z, will keep the default rise and fall time of the TMDS differential output signals as selected by the I2C_EN pin. It is recommended that an external resistor-divider (less than 100 k Ω) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. OVS H Offset 1 DDC source side VOL and VIL offset range 1 L Offset 2 DDC source side VOL and VIL offset range 2 Hi-Z Offset 3 DDC source side VOL and VIL offset range 3 It is recommended that an external resistor-divider (less than 100 k Ω) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. DDC_EN H DDC Buffer DDC Buffer is enabled enabled L DDC buffer DDC Buffer is disabled disabled 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage range(2) VCC –0.3 3.6 V Main Link Input (IN_Dx) differential voltage –0.3 VCC + 0.3 V TMDS Outputs (OUT_Dx) –0.3 VCC + 0.3 Voltage range HPD_SOURCE, SDA_SOURCE, SCL_SOURCE, OVS, DDC_EN, VSadj, –0.3 VCC + 0.3 SRC, I2C_EN HPD_SINK, SDA_SINK, SCL_SINK, OE_EN, HPDINV –0.3 5.5 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. 6.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –55 150 °C Human body model(1) –10 10 kV V(ESD) Electrostatic discharge Charged-device model(2) –1.5 1.5 Machine model(3) –200 200 V (1) Tested in accordance with JEDEC Standard 22, Test Method A114-B (2) Tested in accordance with JEDEC Standard 22, Test Method C101-A (3) Tested in accordance with JEDEC Standard 22, Test Method A115-A 6 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: SN75DP139 |
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