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LMF100CIWM Datasheet(PDF) 3 Page - Texas Instruments |
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LMF100CIWM Datasheet(HTML) 3 Page - Texas Instruments |
3 / 42 page Not Recommended for New Designs LMF100 www.ti.com SNOSBG9B – JULY 1999 – REVISED JUNE 2015 5 Pin Configuration and Functions DW and N Package 20-Pin SOIC and PDIP (N20 or M20B) (Top View) Pin Functions PIN I/O DESCRIPTION NAME NO. 1 LP 20 The second order lowpass, bandpass and notch, allpass and highpass outputs. These outputs can typically swing to 2 BP I/O within 1 V of each supply when driving a 5-k Ω load. For optimum performance, capacitive loading on these outputs 19 should be minimized. For signal frequencies above 15 kHz, the capacitance loading should be kept below 30 pF. 3 N/AP/HP 18 4 The inverting input of the summing op-amp of each filter. These are high impedance inputs. The noninverting input is INV I internally tied to AGND so the opamp can be used only as an inverting amplifier. 17 5 S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/fCLK x 1 pF. The pin should be driven with S1 I a source impedance of less than 1 k Ω. If S1 is not driven with a signal it should be tied to AGND (mid-supply). 16 This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (SA/B tied to V −) SA/B 6 I or to the lowpass (LP) output (SA/B tied to V +). This offers the flexibility needed for configuring the filter in its various modes of operation. 7(1) I This is both the analog and digital positive supply. VA + Analog and digital negative supplies. VA – and V D – should be derived from the same source. They have been brought out 8(1) I VD + separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and bypassed with a single capacitor. 14 VA – Analog and digital negative supplies. VA – and V D – should be derived from the same source. They have been brought out I separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and 13 VD – bypassed with a single capacitor. Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5-V supplies and CMOS (±5 V) or TTL (0 V–5 V) clock levels, LSh should be tied to system ground. For 0-V to 10-V single-supply operation the AGND pin should be biased at +5 V and the LSh pin should be tied to the LSh 9 I system ground for TTL clock levels. LSh should be biased at +5 V for ±5-V CMOS clock levels. The LSh pin is tied to system ground for ±2.5V operation. For single 5V operation the LSh and VD + pins are tied to system ground for TTL clock levels. 10 Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%, CLK I especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to 11 settle, which yields optimum filter performance. By tying this pin to V+ a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system 50/100 12(1) I ground with dual supplies) or to V– allows the filter to operate at a 100:1 clock to center frequency ratio. This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to AGND 15 I mid-supply for single-supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided. (1) This device is pin-for-pin compatible with the MF10 except for the following changes: (a) Unlike the MF10, the LMF100 has a single positive supply pin (VA +). (b) On the LMF100 VD + is a control pin and is not the digital positive supply as on the MF10. (c) Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V– the LMF100 will remain in the 100:1 mode. Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMF100 |
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