Not Recommended for New Designs

LMF100

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SNOSBG9B – JULY 1999 – REVISED JUNE 2015

5 Pin Configuration and Functions

DW and N Package

20-Pin SOIC and PDIP (N20 or M20B)

(Top View)

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

1

LP

20

The second order lowpass, bandpass and notch, allpass and highpass outputs. These outputs can typically swing to

2

BP

I/O

within 1 V of each supply when driving a 5-k

Ω load. For optimum performance, capacitive loading on these outputs

19

should be minimized. For signal frequencies above 15 kHz, the capacitance loading should be kept below 30 pF.

3

N/AP/HP

18

4

The inverting input of the summing op-amp of each filter. These are high impedance inputs. The noninverting input is

INV

I

internally tied to AGND so the opamp can be used only as an inverting amplifier.

17

5

S1

I

a source impedance of less than 1 k

Ω. If S1 is not driven with a signal it should be tied to AGND (mid-supply).

16

6

I

modes of operation.

I

This is both the analog and digital positive supply.

+

D

I

+

separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and

bypassed with a single capacitor.

14

–

D

I

separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and

13

–

bypassed with a single capacitor.

Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5-V

supplies and CMOS (±5 V) or TTL (0 V–5 V) clock levels, LSh should be tied to system ground.

For 0-V to 10-V single-supply operation the AGND pin should be biased at +5 V and the LSh pin should be tied to the

LSh

9

I

system ground for TTL clock levels. LSh should be biased at +5 V for ±5-V CMOS clock levels.

system ground for TTL clock levels.

10

Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK

inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%,

CLK

I

especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to

11

settle, which yields optimum filter performance.

By tying this pin to V+ a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system

50/100

I

This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to

AGND

15

I

mid-supply for single-supply operation. For a further discussion of mid-supply biasing techniques see the Applications

Information (Section 3.2). For optimum filter performance a “clean” ground must be provided.

(1)

This device is pin-for-pin compatible with the MF10 except for the following changes:

in the 100:1 mode.

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