SN54LVT8980A, SN74LVT8980A

EMBEDDED TEST BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8BIT GENERIC HOST INTERFACES

SCBS755B − APRIL 2002 − REVISED MARCH 2004

5

POST OFFICE BOX 655303

application information

In application, the eTBC is used to master a single IEEE Std 1149.1 TAP under the control of a

microprocessor/microcontroller host. A typical implementation is shown in Figure 1.

IEEE

Std 1149.1-

Compliant

Device Chain

(Target)

TRST

RST

STRB

R/W

RDY

A2−A0

D7−D0

TDI

TDO

TMS

TCK

’LVT8980A

eTBC

Microprocessor/

Microcontroller

(Host)

Program/Vector

Memory

(ROM/RAM)

(If/As Required)

OSC

CLKIN

TOE

CS

GND

Figure 1. eTBC Application

All signals required to master IEEE Std 1149.1-compliant devices—TCK, TMS, TDO, TDI—are

sourced/received by the eTBC. The eTBC also can source the optional TRST signal. Additionally, the eTBC

implements high-drive output buffers, allowing it to interface directly to on- or off-board targets without need for

buffering or other additional logic.

The eTBC generic host interface allows it to act as a simple 8-bit memory- or I/O-mapped peripheral. As shown

in Figure 1, for many choices of host microprocessor/microcontroller, this interface can be accomplished without

additional logic. While the eTBC requires a clock input (CLKIN), in many cases it can be driven from the same

source that provides a clock signal to the host.

Thus, in combination with the host microprocessor/microcontroller, the eTBC can be used to implement a

two-chip embedded test control function supporting board- and system-level built-in test based on structured

IEEE Std 1149.1 test access. In some cases, for additional program and/or test vector storage, an external

ROM/RAM may be required.

By use of the eTBC in such an embedded test control function, the host microprocessor/microcontroller is freed

from the burden of generating the TAP-state sequences, serializing the outgoing bit stream, and deserializing

the incoming bit stream. All such tasks are implemented in the eTBC, allowing the host to operate at full 8-bit

parallel efficiency, host software to operate at the level of discrete scan operations versus the level of TAP

manipulation, and test throughput to be maximized. The eTBC’s full suite of data-scan and instruction-scan

commands ensure that the host software operates efficiently.

Host efficiency and flexibility also is maximized through the eTBC’s fully visible status and implementation of

the ready (RDY) output. RDY goes inactive during a read or write access if the host-requested access cannot

be performed immediately. Thus, it can be used to insert hold or wait states back to the host. When the condition

blocking the access clears, the requested access completes. Additionally, all conditions that can cause such

a blocking condition are updated continuously in the eTBC status and command registers. Thus, the host

software can poll the eTBC status, rather than implement RDY in hardware.