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P4C1024-15J3I Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C1024-15J3I Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 8 page Document # SRAM124 REV A Revised October 2005 P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM The P4C1024 device provides asynchronous opera- tions with matching access and cycle times. Memory locations are specified on address pins A 0 to A16. Reading is accomplished by device selection (CE 1 low and CE 2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the ad- dress under these conditions, the data in the ad- dressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE 1 or OE is HIGH or WE or CE 2 is LOW. The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 15 nanoseconds permit greatly en- hanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1024 is a member of a family of PACE RAM™ products offer- ing fast access times. Advanced CMOS Technology Fast t OE Automatic Power Down Packages —32-Pin 300 mil DIP and SOJ —32-Pin 400 mil SOJ —32-Pin 600 mil Ceramic DIP —32-Pin 400 mil Ceramic DIP —32-Pin Solder Seal Flatpack —32-Pin LCC (450 x 500 mil) —32-Pin Ceramic SOJ High Speed (Equal Access and Cycle Times) — 15/20/25/35 ns (Commercial) — 20/25/35/45 ns (Industrial) — 20/25/35/45/55/70/85/100/120 ns (Military) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE CE CE CE CE 1, CE2 and OE OE OE OE OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DESCRIPTION FEATURES DIP (P300, C10, C11), SOJ (J300, J400, CJ1), SOLDER SEAL FLATPACK (FS-3) SIMILAR LCC (L6) |
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