SN65C1406, SN75C1406

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148E – MAY 1990 – REVISED OCTOBER 2001

5

POST OFFICE BOX 655303

DRIVER SECTION

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High level output voltage

VIH = 0.8 V,

RL = 3 kΩ,

VDD = 5 V,

VSS = – 5 V

4

4.5

V

VOH

High-level output voltage

IH

,

See Figure 1

VDD = 12 V,

VSS = – 12 V

10

10.8

V

VOL

Low-level output voltage

VIH = 2 V,

RL = 3 kΩ,

VDD = 5 V,

VSS = – 5 V

–4.4

–4

V

VOL

g

(see Note 3)

IH

,

See Figure 1

VDD = 12 V,

VSS = – 12 V

–10.7

–10

V

IIH

High-level input current

VI = 5 V,

See Figure 2

1

µA

IIL

Low-level input current

VI = 0,

See Figure 2

–1

µA

IOS(H)

High-level short-circuit

output current‡

VI = 0.8 V,

VO = 0 or VSS,

See Figure 1

–7.5

–12

–19.5

mA

IOS(L)

Low-level short-circuit

output current‡

VI = 2 V,

VO = 0 or VDD,

See Figure 1

7.5

12

19.5

mA

IDD

Supply current from VDD

No load,

VDD = 5 V,

VSS = – 5 V

115

250

µA

IDD

Supply current from VDD

,

All inputs at 2 V or 0.8 V

VDD = 12 V,

VSS = – 12 V

115

250

µA

ISS

Supply current from VSS

No load,

VDD = 5 V,

VSS = – 5 V

–115

–250

µA

ISS

Supply current from VSS

,

All inputs at 2 V or 0.8 V

VDD = 12 V,

VSS = – 12 V

–115

–250

µA

rO

Output resistance

VDD = VSS = VCC = 0,

See Note 4

VO = – 2 V to 2 V,

300

400

Ω

† All typical values are at TA = 25°C.

‡ Not more than one output should be shorted at a time.

NOTES:

3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic

levels only.

4. Test conditions are those specified by TIA/EIA-232-F.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH Propagation delay time, low- to high-level output§

RL = 3 kΩ to 7 kΩ,CL = 15 pF,

See Figure 3

1.2

3

µs

tPHL Propagation delay time, high- to low-level output§

RL = 3 kΩ to 7 kΩ,CL = 15 pF,

See Figure 3

2.5

3.5

µs

tTLH Transition time, low- to high-level output¶

RL = 3 kΩ to 7 kΩ,CL = 15 pF,

See Figure 3

0.53

2

3.2

µs

tTHL Transition time, high- to low-level output¶

RL = 3 kΩ to 7 kΩ,CL = 15 pF,

See Figure 3

0.53

2

3.2

µs

tTLH Transition time, low- to high-level output#

RL = 3 kΩ to 7 kΩ,CL = 2500 pF,

See Figure 3

1

2

µs

tTHL Transition time, high- to low-level output#

RL = 3 kΩ to 7 kΩ,CL = 2500 pF,

See Figure 3

1

2

µs

SR

Output slew rate

RL = 3 kΩ to 7 kΩ,CL = 15 pF,

See Figure 3

4

10

30

V/

µs

§ tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.

¶ Measured between 10% and 90% points of output waveform

# Measured between 3-V and – 3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low